79e6b0e0f6
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>. This patch proposes to then include <zephyr/kernel.h> instead of <zephyr/zephyr.h> since it is more clear that you are including the Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a catch-all header that may be confusing. Most applications need to include a bunch of other things to compile, e.g. driver headers or subsystem headers like BT, logging, etc. The idea of a catch-all header in Zephyr is probably not feasible anyway. Reason is that Zephyr is not a library, like it could be for example `libpython`. Zephyr provides many utilities nowadays: a kernel, drivers, subsystems, etc and things will likely grow. A catch-all header would be massive, difficult to keep up-to-date. It is also likely that an application will only build a small subset. Note that subsystem-level headers may use a catch-all approach to make things easier, though. NOTE: This patch is **NOT** removing the header, just removing its usage in-tree. I'd advocate for its deprecation (add a #warning on it), but I understand many people will have concerns. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
126 lines
3.1 KiB
C
126 lines
3.1 KiB
C
/*
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include "codec.h"
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#include <zephyr/sys/printk.h>
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#include <zephyr/drivers/i2c.h>
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#if DT_ON_BUS(WM8731_NODE, i2c)
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#define WM8731_I2C_NODE DT_BUS(WM8731_NODE)
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#define WM8731_I2C_ADDR DT_REG_ADDR(WM8731_NODE)
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bool init_wm8731_i2c(void)
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{
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const struct device *const i2c_dev = DEVICE_DT_GET(WM8731_I2C_NODE);
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/* Initialization data for WM8731 registers. */
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static const uint8_t init[][2] = {
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/*
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* Reset Register:
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* [8:0] RESET = 0 (reset device)
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*/
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{ 0x1E, 0x00 },
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/*
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* Power Down Control:
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* [7] POWEROFF = 0 (Disable POWEROFF)
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* [6] CLKOUTPD = 1 (Enable Power Down)
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* [5] OSCPDD = 0 (Disable Power Down)
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* [4] OUTPD = 1 (Enable Power Down)
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* [3] DACPD = 0 (Disable Power Down)
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* [2] ADCPD = 0 (Disable Power Down)
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* [1] MICPD = 1 (Enable Power Down)
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* [0] LINEINPD = 0 (Disable Power Down)
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*/
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{ 0x0C, 0x52 },
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/*
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* Left Line In:
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* [8] LRINBOTH = 1 (Enable Simultaneous Load)
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* [7] LINMUTE = 0 (Disable Mute)
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* [4:0] LINVOL = 0x07 (-24 dB)
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*/
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{ 0x01, 0x07 },
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/*
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* Left Headphone Out:
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* [8] LRHPBOTH = 1 (Enable Simultaneous Load)
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* [7] LZCEN = 0 (Disable)
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* [6:0] LHPVOL = 0x79 (0 dB)
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*/
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{ 0x05, 0x79 },
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/*
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* Analogue Audio Path Control:
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* [7:6] SIDEATT = 0 (-6 dB)
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* [5] SIDETONE = 0 (Disable Side Tone)
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* [4] DACSEL = 1 (Select DAC)
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* [3] BYPASS = 0 (Disable Bypass)
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* [2] INSEL = 0 (Line Input Select to ADC)
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* [1] MUTEMIC = 1 (Enable Mute)
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* [0] MICBOOST = 0 (Disable Boost)
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*/
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{ 0x08, 0x12 },
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/*
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* Digital Audio Path Control:
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* [4] HPOR = 0 (clear offset)
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* [3] DACMU = 0 (Disable soft mute)
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* [2:1] DEEMP = 0 (Disable)
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* [0] ADCHPD = 1 (Disable High Pass Filter)
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*/
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{ 0x0A, 0x01 },
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/*
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* Digital Audio Interface Format:
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* [7] BCLKINV = 0 (Don't invert BCLK)
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* [6] MS = 0 (Enable Slave Mode)
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* [5] LRSWAP = 0 (Right Channel DAC Data Right)
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* [4] LRP = 1 (Right Channel DAC data when DACLRC high)
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* [3:2] IWL = 0 (16 bits)
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* [1:0] FORMAT = 2 (I2S Format)
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*/
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{ 0x0E, 0x12 },
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/*
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* Sampling Control:
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* [7] CLKODIV2 = 0 (CLOCKOUT is Core Clock)
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* [6] CLKIDIV2 = 0 (Core Clock is MCLK)
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* [5:2] SR = 0x8 (44.1 kHz)
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* [1] BOSR = 0 (256fs)
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* [0] USB/NORMAL = 0 (Normal mode)
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*/
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{ 0x10, 0x20 },
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/*
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* Active Control:
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* [0] ACTIVE = 1 (Active)
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*/
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{ 0x12, 0x01 },
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/*
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* As recommended in WAN_0111, set the OUTPD bit in the Power
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* Down Control register to 0 at the very end of the power-on
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* sequence.
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*/
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{ 0x0C, 0x42 }
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};
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if (!device_is_ready(i2c_dev)) {
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printk("%s is not ready\n", i2c_dev->name);
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return false;
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}
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for (int i = 0; i < ARRAY_SIZE(init); ++i) {
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const uint8_t *entry = init[i];
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int ret;
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ret = i2c_reg_write_byte(i2c_dev, WM8731_I2C_ADDR,
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entry[0], entry[1]);
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if (ret < 0) {
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printk("Initialization step %d failed\n", i);
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return false;
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}
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}
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return true;
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}
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#endif /* DT_ON_BUS(WM8731_NODE, i2c) */
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