8fb592dfff
The symbol DCACHE_LINE_SIZE was not being defined in Intel ADSP targets. It fixes the following problem: /zephyr/soc/intel/intel_adsp/ace/power.c:30:29: error: 'CONFIG_DCACHE_LINE_SIZE' undeclared here (not in a function); did you mean 'XCHAL_DCACHE_LINESIZE'? 30 | uint8_t adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE] __aligned(CONFIG_DCACHE_LINE_SIZE); Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
55 lines
915 B
Plaintext
55 lines
915 B
Plaintext
# Intel CAVS SoC family default configuration options
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#
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# Copyright (c) 2020-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_INTEL_ADSP
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rsource "*/Kconfig.defconfig.series"
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# A workaround for HWMv2 to recover SOF arch/xtensa defaults overridden by arch/host.
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if SOF
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config CORE_COUNT
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int
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default MP_MAX_NUM_CPUS
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endif
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config XTENSA_RPO_CACHE
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def_bool y
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# console can't handle the amount of data coming from many tests, so introduce
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# a delay beween testcases.
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if ZTEST
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config ZTEST_TEST_DELAY_MS
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default 100
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endif
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if XTENSA_RPO_CACHE
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config XTENSA_CACHED_REGION
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default 5
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config XTENSA_UNCACHED_REGION
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default 4
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endif # XTENSA_RPO_CACHE
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config CONSOLE
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def_bool y
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if CONSOLE
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config WINSTREAM_CONSOLE
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def_bool y
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endif
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config CACHE_MANAGEMENT
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def_bool y
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choice CACHE_TYPE
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default ARCH_CACHE
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endchoice
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config DCACHE_LINE_SIZE
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default 64
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endif # SOC_FAMILY_INTEL_ADSP
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