42fb9067e4
This commit updates the riscv_machine_timer driver to resolve MTIME and MTIMECMP register addresses by their `reg-names` instead of relying on index order. This improves clarity and robustness in DTS bindings, and is a prerequisite for handling cases where not both MTIME and MTIMECMP registers are present or accessible. Signed-off-by: Chen Xingyu <hi@xingrz.me>
17 lines
296 B
YAML
17 lines
296 B
YAML
# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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description: RISC-V Machine Timer.
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compatible: "riscv,machine-timer"
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include: base.yaml
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properties:
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reg:
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required: true
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reg-names:
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required: true
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interrupts-extended:
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required: true
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