e0f02d93a6
Two DMA channels are assigned to AES channels A and B respectively. Each channel A/B has an interface to control the conditions that will generate requests on the related DMA channel: trigger condition, R/W address, and DMA done action. Signed-off-by: Julien Panis <jpanis@baylibre.com> |
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| .. | ||
| arm,cryptocell-310.yaml | ||
| arm,cryptocell-312.yaml | ||
| atmel,ataes132a.yaml | ||
| intel,adsp-sha.yaml | ||
| ite,it8xxx2-sha-v2.yaml | ||
| ite,it8xxx2-sha.yaml | ||
| ite,it51xxx-sha.yaml | ||
| microchip,xec-symcr.yaml | ||
| nordic,nrf-ccm.yaml | ||
| nordic,nrf-ecb.yaml | ||
| nuvoton,npcx-sha.yaml | ||
| nxp,mcux-dcp.yaml | ||
| realtek,rts5912-sha.yaml | ||
| renesas,smartbond-crypto.yaml | ||
| silabs,gecko-semailbox.yaml | ||
| silabs,si32-aes.yaml | ||
| st,stm32-aes.yaml | ||
| st,stm32-cryp.yaml | ||
| st,stm32-crypto-common.yaml | ||
| st,stm32l4-aes.yaml | ||
| ti,cc23x0-aes.yaml | ||