86b31465f4
Add minimal support for the aesc silicon UART IP core. This core includes an internal clock divider and supports flexible frame configurations, allowing for variable data length, parity, and stop bit settings. The current driver version does not support interrupts. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
11 lines
243 B
Plaintext
11 lines
243 B
Plaintext
# Copyright (c) 2025 Aesc Silicon
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# SPDX-License-Identifier: Apache-2.0
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config UART_AESC
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bool "Aesc Silicon UART driver"
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default y
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depends on DT_HAS_AESC_UART_ENABLED
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select SERIAL_HAS_DRIVER
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help
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Enable the Aesc Silicon UART driver.
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