b31eeb6c6e
Add a generic driver for MSPI controllers based on the DesignWare SSI core. With small vendor-specific adaptations covering integration details, it should be possible to use the driver for various devices. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
240 lines
8.0 KiB
C
240 lines
8.0 KiB
C
/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* This header is part of mspi_dw.c extracted only for clarity.
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* It is not supposed to be included by any file other than mspi_dw.c.
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*/
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/* CTRLR0 - Control Register 0 */
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#define CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
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#define CTRLR0_SPI_FRF_STANDARD 0UL
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#define CTRLR0_SPI_FRF_DUAL 1UL
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#define CTRLR0_SPI_FRF_QUAD 2UL
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#define CTRLR0_SPI_FRF_OCTAL 3UL
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#define CTRLR0_TMOD_MASK GENMASK(11, 10)
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#define CTRLR0_TMOD_TX_RX 0UL
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#define CTRLR0_TMOD_TX 1UL
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#define CTRLR0_TMOD_RX 2UL
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#define CTRLR0_TMOD_EEPROM 3UL
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#define CTRLR0_SCPOL_BIT BIT(9)
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#define CTRLR0_SCPH_BIT BIT(8)
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#define CTRLR0_FRF_MASK GENMASK(7, 6)
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#define CTRLR0_FRF_SPI 0UL
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#define CTRLR0_FRF_SSP 1UL
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#define CTRLR0_FRF_MICROWIRE 2UL
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#define CTRLR0_DFS_MASK GENMASK(4, 0)
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/* CTRLR1- Control Register 1 */
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#define CTRLR1_NDF_MASK GENMASK(15, 0)
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/* SSIENR - SSI Enable Register */
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#define SSIENR_SSIC_EN_BIT BIT(0)
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/* TXFTLR - Transmit FIFO Threshold Level */
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#define TXFTLR_TXFTHR_MASK GENMASK(23, 16)
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#define TXFTLR_TFT_MASK GENMASK(7, 0)
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/* RXFTLR - Receive FIFO Threshold Level */
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#define RXFTLR_RFT_MASK GENMASK(7, 0)
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/* TXFLR - Transmit FIFO Level Register */
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#define TXFLR_TXTFL_MASK GENMASK(7, 0)
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/* RXFLR - Receive FIFO Level Register */
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#define RXFLR_RXTFL_MASK GENMASK(7, 0)
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/* SR - Status Register */
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#define SR_BUSY_BIT BIT(0)
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/* IMR - Interrupt Mask Register */
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#define IMR_TXEIM_BIT BIT(0)
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#define IMR_TXOIM_BIT BIT(1)
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#define IMR_RXUIM_BIT BIT(2)
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#define IMR_RXOIM_BIT BIT(3)
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#define IMR_RXFIM_BIT BIT(4)
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#define IMR_MSTIM_BIT BIT(5)
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/* ISR - Interrupt Status Register */
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#define ISR_TXEIS_BIT BIT(0)
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#define ISR_TXOIS_BIT BIT(1)
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#define ISR_RXUIS_BIT BIT(2)
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#define ISR_RXOIS_BIT BIT(3)
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#define ISR_RXFIS_BIT BIT(4)
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#define ISR_MSTIS_BIT BIT(5)
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/* SPI_CTRLR0 - SPI Control Register */
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#define SPI_CTRLR0_CLK_STRETCH_EN_BIT BIT(30)
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#define SPI_CTRLR0_XIP_PREFETCH_EN_BIT BIT(29)
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#define SPI_CTRLR0_XIP_MBL_BIT BIT(26)
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#define SPI_CTRLR0_SPI_RXDS_SIG_EN_BIT BIT(25)
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#define SPI_CTRLR0_SPI_DM_EN_BIT BIT(24)
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#define SPI_CTRLR0_RXDS_VL_EN_BIT BIT(23)
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#define SPI_CTRLR0_SSIC_XIP_CONT_XFER_EN_BIT BIT(21)
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#define SPI_CTRLR0_XIP_INST_EN_BIT BIT(20)
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#define SPI_CTRLR0_XIP_DFS_HC_BIT BIT(19)
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#define SPI_CTRLR0_SPI_RXDS_EN_BIT BIT(18)
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#define SPI_CTRLR0_INST_DDR_EN_BIT BIT(17)
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#define SPI_CTRLR0_SPI_DDR_EN_BIT BIT(16)
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#define SPI_CTRLR0_WAIT_CYCLES_MASK GENMASK(15, 11)
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#define SPI_CTRLR0_WAIT_CYCLES_MAX BIT_MASK(5)
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#define SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
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#define SPI_CTRLR0_INST_L0 0UL
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#define SPI_CTRLR0_INST_L4 1UL
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#define SPI_CTRLR0_INST_L8 2UL
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#define SPI_CTRLR0_INST_L16 3UL
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#define SPI_CTRLR0_XIP_MD_BIT_EN_BIT BIT(7)
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#define SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
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#define SPI_CTRLR0_TRANS_TYPE_MASK GENMASK(1, 0)
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#define SPI_CTRLR0_TRANS_TYPE_TT0 0UL
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#define SPI_CTRLR0_TRANS_TYPE_TT1 1UL
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#define SPI_CTRLR0_TRANS_TYPE_TT2 2UL
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#define SPI_CTRLR0_TRANS_TYPE_TT3 3UL
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/* XIP_CTRL - XIP Control Register */
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#define XIP_CTRL_XIP_PREFETCH_EN_BIT BIT(28)
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#define XIP_CTRL_XIP_MBL_MASK GENMASK(27, 26)
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#define XIP_CTRL_XIP_MBL_2 0UL
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#define XIP_CTRL_XIP_MBL_4 1UL
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#define XIP_CTRL_XIP_MBL_8 2UL
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#define XIP_CTRL_XIP_MBL_16 3UL
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#define XIP_CTRL_RXDS_SIG_EN_BIT BIT(25)
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#define XIP_CTRL_XIP_HYBERBUS_EN_BIT BIT(24)
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#define XIP_CTRL_CONT_XFER_EN_BIT BIT(23)
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#define XIP_CTRL_INST_EN_BIT BIT(22)
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#define XIP_CTRL_RXDS_EN_BIT BIT(21)
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#define XIP_CTRL_INST_DDR_EN_BIT BIT(20)
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#define XIP_CTRL_DDR_EN_BIT BIT(19)
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#define XIP_CTRL_DFS_HC_BIT BIT(18)
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#define XIP_CTRL_WAIT_CYCLES_MASK GENMASK(17, 13)
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#define XIP_CTRL_WAIT_CYCLES_MAX BIT_MASK(5)
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#define XIP_CTRL_MD_BITS_EN_BIT BIT(12)
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#define XIP_CTRL_INST_L_MASK GENMASK(10, 9)
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#define XIP_CTRL_INST_L0 0UL
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#define XIP_CTRL_INST_L4 1UL
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#define XIP_CTRL_INST_L8 2UL
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#define XIP_CTRL_INST_L16 3UL
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#define XIP_CTRL_ADDR_L_MASK GENMASK(7, 4)
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#define XIP_CTRL_TRANS_TYPE_MASK GENMASK(3, 2)
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#define XIP_CTRL_TRANS_TYPE_TT0 0UL
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#define XIP_CTRL_TRANS_TYPE_TT1 1UL
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#define XIP_CTRL_TRANS_TYPE_TT2 2UL
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#define XIP_CTRL_FRF_MASK GENMASK(1, 0)
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#define XIP_CTRL_FRF_DUAL 1UL
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#define XIP_CTRL_FRF_QUAD 2UL
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#define XIP_CTRL_FRF_OCTAL 3UL
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/* XIP_CTRL - XIP Control Register */
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#define XIP_CTRL_XIP_PREFETCH_EN_BIT BIT(28)
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#define XIP_CTRL_XIP_MBL_MASK GENMASK(27, 26)
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#define XIP_CTRL_XIP_MBL_2 0UL
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#define XIP_CTRL_XIP_MBL_4 1UL
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#define XIP_CTRL_XIP_MBL_8 2UL
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#define XIP_CTRL_XIP_MBL_16 3UL
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#define XIP_CTRL_XIP_HYBERBUS_EN_BIT BIT(24)
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#define XIP_CTRL_CONT_XFER_EN_BIT BIT(23)
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#define XIP_CTRL_INST_EN_BIT BIT(22)
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#define XIP_CTRL_RXDS_EN_BIT BIT(21)
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#define XIP_CTRL_INST_DDR_EN_BIT BIT(20)
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#define XIP_CTRL_DDR_EN_BIT BIT(19)
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#define XIP_CTRL_DFS_HC_BIT BIT(18)
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/* XIP_WRITE_CTRL - XIP Write Control Register */
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#define XIP_WRITE_CTRL_WAIT_CYCLES_MASK GENMASK(20, 16)
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#define XIP_WRITE_CTRL_WAIT_CYCLES_MAX BIT_MASK(5)
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#define XIP_WRITE_CTRL_RXDS_SIG_EN_BIT BIT(13)
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#define XIP_WRITE_CTRL_HYBERBUS_EN_BIT BIT(12)
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#define XIP_WRITE_CTRL_INST_DDR_EN_BIT BIT(11)
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#define XIP_WRITE_CTRL_SPI_DDR_EN_BIT BIT(10)
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#define XIP_WRITE_CTRL_INST_L_MASK GENMASK(9, 8)
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#define XIP_WRITE_CTRL_INST_L0 0UL
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#define XIP_WRITE_CTRL_INST_L4 1UL
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#define XIP_WRITE_CTRL_INST_L8 2UL
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#define XIP_WRITE_CTRL_INST_L16 3UL
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#define XIP_WRITE_CTRL_ADDR_L_MASK GENMASK(7, 4)
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#define XIP_WRITE_CTRL_TRANS_TYPE_MASK GENMASK(3, 2)
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#define XIP_WRITE_CTRL_TRANS_TYPE_TT0 0UL
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#define XIP_WRITE_CTRL_TRANS_TYPE_TT1 1UL
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#define XIP_WRITE_CTRL_TRANS_TYPE_TT2 2UL
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#define XIP_WRITE_CTRL_FRF_MASK GENMASK(1, 0)
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#define XIP_WRITE_CTRL_FRF_DUAL 1UL
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#define XIP_WRITE_CTRL_FRF_QUAD 2UL
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#define XIP_WRITE_CTRL_FRF_OCTAL 3UL
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/* Register access helpers. */
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#define USES_AUX_REG(inst) + DT_INST_PROP(inst, aux_reg_enable)
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#define AUX_REG_INSTANCES (0 DT_INST_FOREACH_STATUS_OKAY(USES_AUX_REG))
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#define BASE_ADDR(dev) (mm_reg_t)DEVICE_MMIO_GET(dev)
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#if AUX_REG_INSTANCES != 0
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static uint32_t aux_reg_read(const struct device *dev, uint32_t off)
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{
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return sys_in32(BASE_ADDR(dev) + off/4);
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}
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static void aux_reg_write(uint32_t data, const struct device *dev, uint32_t off)
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{
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sys_out32(data, BASE_ADDR(dev) + off/4);
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}
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#endif
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#if AUX_REG_INSTANCES != DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)
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static uint32_t reg_read(const struct device *dev, uint32_t off)
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{
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return sys_read32(BASE_ADDR(dev) + off);
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}
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static void reg_write(uint32_t data, const struct device *dev, uint32_t off)
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{
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sys_write32(data, BASE_ADDR(dev) + off);
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}
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#endif
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#if AUX_REG_INSTANCES == 0
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/* If no instance uses aux-reg access. */
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#define DECLARE_REG_ACCESS()
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#define DEFINE_REG_ACCESS(inst)
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#define DEFINE_MM_REG_RD(reg, off) \
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static inline uint32_t read_##reg(const struct device *dev) \
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{ return reg_read(dev, off); }
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#define DEFINE_MM_REG_WR(reg, off) \
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static inline void write_##reg(const struct device *dev, uint32_t data) \
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{ reg_write(data, dev, off); }
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#elif AUX_REG_INSTANCES == DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)
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/* If all instances use aux-reg access. */
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#define DECLARE_REG_ACCESS()
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#define DEFINE_REG_ACCESS(inst)
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#define DEFINE_MM_REG_RD(reg, off) \
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static inline uint32_t read_##reg(const struct device *dev) \
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{ return aux_reg_read(dev, off); }
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#define DEFINE_MM_REG_WR(reg, off) \
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static inline void write_##reg(const struct device *dev, uint32_t data) \
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{ aux_reg_write(data, dev, off); }
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#else
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/* If register access varies by instance. */
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#define DECLARE_REG_ACCESS() \
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uint32_t (*read)(const struct device *dev, uint32_t off); \
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void (*write)(uint32_t data, const struct device *dev, uint32_t off)
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#define DEFINE_REG_ACCESS(inst) \
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COND_CODE_1(DT_INST_PROP(inst, aux_reg_enable), \
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(.read = aux_reg_read, \
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.write = aux_reg_write,), \
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(.read = reg_read, \
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.write = reg_write,))
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#define DEFINE_MM_REG_RD(reg, off) \
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static inline uint32_t read_##reg(const struct device *dev) \
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{ \
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const struct mspi_dw_config *dev_config = dev->config; \
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return dev_config->read(dev, off); \
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}
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#define DEFINE_MM_REG_WR(reg, off) \
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static inline void write_##reg(const struct device *dev, uint32_t data) \
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{ \
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const struct mspi_dw_config *dev_config = dev->config; \
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dev_config->write(data, dev, off); \
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}
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#endif
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