88d8003109
Add enabled_clock, on / off and configure support for the clocks of the stm32mp13. Describes the peripheral clock source selection. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
295 lines
8.1 KiB
C
295 lines
8.1 KiB
C
/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_system.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/sys/util.h>
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/** @brief Verifies clock is part of active clock configuration */
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int enabled_clock(uint32_t src_clk)
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{
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if ((src_clk == STM32_SRC_HSE && IS_ENABLED(STM32_HSE_ENABLED)) ||
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(src_clk == STM32_SRC_HSI && IS_ENABLED(STM32_HSI_ENABLED)) ||
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(src_clk == STM32_SRC_LSE && IS_ENABLED(STM32_LSE_ENABLED)) ||
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(src_clk == STM32_SRC_LSI && IS_ENABLED(STM32_LSI_ENABLED)) ||
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(src_clk == STM32_SRC_PLL1_P && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL2_P && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL2_Q && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
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(src_clk == STM32_SRC_PLL2_R && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
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(src_clk == STM32_SRC_PLL3_P && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL3_Q && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
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(src_clk == STM32_SRC_PLL3_R && IS_ENABLED(STM32_PLL3_R_ENABLED)) ||
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(src_clk == STM32_SRC_PLL4_P && IS_ENABLED(STM32_PLL4_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL4_Q && IS_ENABLED(STM32_PLL4_Q_ENABLED)) ||
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(src_clk == STM32_SRC_PLL4_R && IS_ENABLED(STM32_PLL4_R_ENABLED))) {
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return 0;
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}
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return -ENOTSUP;
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}
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static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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volatile int temp;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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/* Ensure that the write operation is completed */
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temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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UNUSED(temp);
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return 0;
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}
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static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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volatile int temp;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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/* Ensure that the write operation is completed */
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temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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UNUSED(temp);
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return 0;
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}
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static int stm32_clock_control_configure(const struct device *dev,
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clock_control_subsys_t sub_system,
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void *data)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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int err;
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ARG_UNUSED(dev);
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ARG_UNUSED(data);
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err = enabled_clock(pclken->bus);
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if (err < 0) {
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/* Attempt to configure a src clock not available or not valid */
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return err;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
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STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
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STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
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STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
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STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system, uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_APB1:
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switch (pclken->enr) {
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case LL_APB1_GRP1_PERIPH_UART4:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
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break;
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case LL_APB1_GRP1_PERIPH_I2C1:
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case LL_APB1_GRP1_PERIPH_I2C2:
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*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C12_CLKSOURCE);
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break;
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default:
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return -ENOTSUP;
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}
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break;
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case STM32_CLOCK_BUS_APB6:
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switch (pclken->enr) {
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case LL_APB6_GRP1_PERIPH_I2C3:
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*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C3_CLKSOURCE);
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break;
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case LL_APB6_GRP1_PERIPH_I2C4:
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*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C4_CLKSOURCE);
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break;
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case LL_APB6_GRP1_PERIPH_I2C5:
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*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C5_CLKSOURCE);
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break;
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default:
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return -ENOTSUP;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Gated clocks */
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if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
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== pclken->enr) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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} else {
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/* Domain clock sources */
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if (enabled_clock(pclken->bus) == 0) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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}
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}
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static DEVICE_API(clock_control, stm32_clock_control_api) = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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.configure = stm32_clock_control_configure,
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.get_status = stm32_clock_control_get_status,
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};
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static void set_up_fixed_clock_sources(void)
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{
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if (IS_ENABLED(STM32_HSE_ENABLED)) {
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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/* Wait for HSE ready */
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}
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}
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if (IS_ENABLED(STM32_HSI_ENABLED)) {
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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}
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}
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}
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static int stm32_clock_control_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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set_up_fixed_clock_sources();
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#if STM32_SYSCLK_SRC_HSE
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
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while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_HSE) {
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}
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#elif STM32_SYSCLK_SRC_HSI
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSI);
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while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_HSI) {
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}
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#elif STM32_SYSCLK_SRC_PLL
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BUILD_ASSERT(IS_ENABLED(STM32_HSE_ENABLED),
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"STM32MP13 PLL requires HSE to be enabled!");
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/* The default system clock source is HSI, but the bootloader may have switched it. */
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/* Switch back to HSE for clock setup as PLL1 configuration must not be modified */
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/* while active.*/
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
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while ((READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != RCC_MPCKSELR_MPUSRCRDY)) {
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}
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CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) {
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};
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CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) {
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};
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CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) {
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};
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uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
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uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m);
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uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p);
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uint32_t pll1_fracn = DT_PROP(DT_NODELABEL(pll1), fracn);
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LL_RCC_PLL1_SetN(pll1_n);
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while (LL_RCC_PLL1_GetN() != pll1_n) {
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}
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LL_RCC_PLL1_SetM(pll1_m);
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while (LL_RCC_PLL1_GetM() != pll1_m) {
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}
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LL_RCC_PLL1_SetP(pll1_p);
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while (LL_RCC_PLL1_GetP() != pll1_p) {
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}
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LL_RCC_PLL1_SetFRACV(pll1_fracn);
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while (LL_RCC_PLL1_GetFRACV() != pll1_fracn) {
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}
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LL_RCC_PLL1_Enable();
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while (LL_RCC_PLL1_IsReady() != 1) {
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}
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SET_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) {
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};
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_PLL1);
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while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_PLL1) {
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}
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#endif
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return 0;
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}
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
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stm32_clock_control_init,
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NULL,
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NULL, NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&stm32_clock_control_api);
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