ba36bf6c0a
This patch adds a minimal driver for the MAX98091 audio codec. Currently, playback functionality is supported. Co-developed-by: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io> Signed-off-by: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io> Co-developed-by: Tarang Raval <tarang.raval@siliconsignals.io> Signed-off-by: Tarang Raval <tarang.raval@siliconsignals.io> Signed-off-by: Silicon Signals <siliconsignalsforgit@gmail.com>
214 lines
6.9 KiB
C
214 lines
6.9 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Silicon Signals Pvt. Ltd.
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* Author: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io>
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* Author: Tarang Raval <tarang.raval@siliconsignals.io>
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*/
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#ifndef ZEPHYR_INCLUDE_CODEC_MAX98091_H_
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#define ZEPHYR_INCLUDE_CODEC_MAX98091_H_
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/*
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* MAX98091 Register Definitions
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*/
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#define M98091_REG_SOFTWARE_RESET 0x00
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#define M98091_REG_DEVICE_STATUS 0x01
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#define M98091_REG_JACK_STATUS 0x02
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#define M98091_REG_INTERRUPT_S 0x03
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#define M98091_REG_MASTER_CLOCK 0x04
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#define M98091_REG_QUICK_SAMPLE_RATE 0x05
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#define M98091_REG_DAI_INTERFACE 0x06
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#define M98091_REG_DAC_PATH 0x07
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#define M98091_REG_MIC_DIRECT_TO_ADC 0x08
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#define M98091_REG_LINE_TO_ADC 0x09
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#define M98091_REG_ANALOG_MIC_LOOP 0x0A
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#define M98091_REG_ANALOG_LINE_LOOP 0x0B
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#define M98091_REG_RESERVED 0x0C
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#define M98091_REG_LINE_INPUT_CONFIG 0x0D
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#define M98091_REG_LINE_INPUT_LEVEL 0x0E
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#define M98091_REG_INPUT_MODE 0x0F
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#define M98091_REG_MIC1_INPUT_LEVEL 0x10
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#define M98091_REG_MIC2_INPUT_LEVEL 0x11
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#define M98091_REG_MIC_BIAS_VOLTAGE 0x12
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#define M98091_REG_DIGITAL_MIC_ENABLE 0x13
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#define M98091_REG_DIGITAL_MIC_CONFIG 0x14
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#define M98091_REG_LEFT_ADC_MIXER 0x15
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#define M98091_REG_RIGHT_ADC_MIXER 0x16
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#define M98091_REG_LEFT_ADC_LEVEL 0x17
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#define M98091_REG_RIGHT_ADC_LEVEL 0x18
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#define M98091_REG_ADC_BIQUAD_LEVEL 0x19
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#define M98091_REG_ADC_SIDETONE 0x1A
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#define M98091_REG_SYSTEM_CLOCK 0x1B
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#define M98091_REG_CLOCK_MODE 0x1C
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#define M98091_REG_CLOCK_RATIO_NI_MSB 0x1D
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#define M98091_REG_CLOCK_RATIO_NI_LSB 0x1E
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#define M98091_REG_CLOCK_RATIO_MI_MSB 0x1F
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#define M98091_REG_CLOCK_RATIO_MI_LSB 0x20
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#define M98091_REG_MASTER_MODE 0x21
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#define M98091_REG_INTERFACE_FORMAT 0x22
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#define M98091_REG_TDM_CONTROL 0x23
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#define M98091_REG_TDM_FORMAT 0x24
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#define M98091_REG_IO_CONFIGURATION 0x25
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#define M98091_REG_FILTER_CONFIG 0x26
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#define M98091_REG_DAI_PLAYBACK_LEVEL 0x27
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#define M98091_REG_DAI_PLAYBACK_LEVEL_EQ 0x28
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#define M98091_REG_LEFT_HP_MIXER 0x29
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#define M98091_REG_RIGHT_HP_MIXER 0x2A
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#define M98091_REG_HP_CONTROL 0x2B
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#define M98091_REG_LEFT_HP_VOLUME 0x2C
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#define M98091_REG_RIGHT_HP_VOLUME 0x2D
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#define M98091_REG_LEFT_SPK_MIXER 0x2E
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#define M98091_REG_RIGHT_SPK_MIXER 0x2F
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#define M98091_REG_SPK_CONTROL 0x30
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#define M98091_REG_LEFT_SPK_VOLUME 0x31
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#define M98091_REG_RIGHT_SPK_VOLUME 0x32
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#define M98091_REG_DRC_TIMING 0x33
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#define M98091_REG_DRC_COMPRESSOR 0x34
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#define M98091_REG_DRC_EXPANDER 0x35
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#define M98091_REG_DRC_GAIN 0x36
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#define M98091_REG_RCV_LOUTL_MIXER 0x37
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#define M98091_REG_RCV_LOUTL_CONTROL 0x38
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#define M98091_REG_RCV_LOUTL_VOLUME 0x39
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#define M98091_REG_LOUTR_MIXER 0x3A
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#define M98091_REG_LOUTR_CONTROL 0x3B
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#define M98091_REG_LOUTR_VOLUME 0x3C
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#define M98091_REG_JACK_DETECT 0x3D
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#define M98091_REG_INPUT_ENABLE 0x3E
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#define M98091_REG_OUTPUT_ENABLE 0x3F
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#define M98091_REG_LEVEL_CONTROL 0x40
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#define M98091_REG_DSP_FILTER_ENABLE 0x41
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#define M98091_REG_BIAS_CONTROL 0x42
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#define M98091_REG_DAC_CONTROL 0x43
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#define M98091_REG_ADC_CONTROL 0x44
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#define M98091_REG_DEVICE_SHUTDOWN 0x45
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#define M98091_REG_EQUALIZER_BASE 0x46
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#define M98091_REG_RECORD_BIQUAD_BASE 0xAF
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#define M98091_REG_DMIC3_VOLUME 0xBE
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#define M98091_REG_DMIC4_VOLUME 0xBF
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#define M98091_REG_DMIC34_BQ_PREATTEN 0xC0
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#define M98091_REG_RECORD_TDM_SLOT 0xC1
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#define M98091_REG_SAMPLE_RATE 0xC2
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#define M98091_REG_DMIC34_BIQUAD_BASE 0xC3
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#define M98091_REG_REVISION_ID 0xFF
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/* MAX98090 Register Bit Fields */
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/* M98091_REG_SOFTWARE_RESET */
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#define M98091_SWRESET_MASK BIT(7)
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/* M98091_REG_QUICK_SAMPLE_RATE */
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#define M98091_SR_96K_MASK BIT(5)
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#define M98091_SR_32K_MASK BIT(4)
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#define M98091_SR_48K_MASK BIT(3)
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#define M98091_SR_44K1_MASK BIT(2)
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#define M98091_SR_16K_MASK BIT(1)
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#define M98091_SR_8K_MASK BIT(0)
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/* M98091_REG_DAI_INTERFACE */
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#define M98091_RJ_M_MASK BIT(5)
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#define M98091_RJ_S_MASK BIT(4)
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#define M98091_LJ_M_MASK BIT(3)
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#define M98091_LJ_S_MASK BIT(2)
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#define M98091_I2S_M_MASK BIT(1)
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#define M98091_I2S_S_MASK BIT(0)
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/* M98091_REG_SYSTEM_CLOCK */
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#define M98091_PSCLK_DISABLED (0 << 4)
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#define M98091_PSCLK_DIV1 BIT(4)
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#define M98091_PSCLK_DIV2 (2 << 4)
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#define M98091_PSCLK_DIV4 (3 << 4)
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/* M98091_REG_MASTER_MODE */
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#define M98091_MAS_MASK BIT(7)
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/* M98091_REG_INTERFACE_FORMAT */
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#define M98091_RJ_MASK BIT(5)
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#define M98091_WCI_MASK BIT(4)
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#define M98091_BCI_MASK BIT(3)
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#define M98091_DLY_MASK BIT(2)
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#define M98091_WS_MASK (3 << 0)
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#define M98091_16B_WS (0 << 0)
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/* M98091_REG_IO_CONFIGURATION */
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#define M98091_LTEN_MASK BIT(5)
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#define M98091_LBEN_MASK BIT(4)
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#define M98091_DMONO_MASK BIT(3)
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#define M98091_HIZOFF_MASK BIT(2)
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#define M98091_SDOEN_MASK BIT(1)
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#define M98091_SDIEN_MASK BIT(0)
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/* M98091_REG_LEFT_HP_MIXER */
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#define M98091_MIXHPL_MIC2_MASK BIT(5)
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#define M98091_MIXHPL_MIC1_MASK BIT(4)
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#define M98091_MIXHPL_LINEB_MASK BIT(3)
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#define M98091_MIXHPL_LINEA_MASK BIT(2)
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#define M98091_MIXHPL_DACR_MASK BIT(1)
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#define M98091_MIXHPL_DACL_MASK BIT(0)
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#define M98091_MIXHPL_MASK (63 << 0)
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/* M98091_REG_RIGHT_HP_MIXER */
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#define M98091_MIXHPR_MIC2_MASK BIT(5)
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#define M98091_MIXHPR_MIC1_MASK BIT(4)
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#define M98091_MIXHPR_LINEB_MASK BIT(3)
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#define M98091_MIXHPR_LINEA_MASK BIT(2)
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#define M98091_MIXHPR_DACR_MASK BIT(1)
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#define M98091_MIXHPR_DACL_MASK BIT(0)
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#define M98091_MIXHPR_MASK (63 << 0)
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/* M98091_REG_HP_CONTROL */
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#define M98091_MIXHPRSEL_MASK BIT(5)
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#define M98091_MIXHPLSEL_MASK BIT(4)
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#define M98091_MIXHPRG_MASK (3 << 2)
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#define M98091_MIXHPLG_MASK (3 << 0)
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/* M98091_REG_LEFT_HP_VOLUME */
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#define M98091_HPLM_MASK BIT(7)
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#define M98091_HPVOLL_MASK (31 << 0)
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/* M98091_REG_LEFT_SPK_MIXER */
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#define M98091_MIXSPL_MIC2_MASK BIT(5)
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#define M98091_MIXSPL_MIC1_MASK BIT(4)
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#define M98091_MIXSPL_LINEB_MASK BIT(3)
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#define M98091_MIXSPL_LINEA_MASK BIT(2)
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#define M98091_MIXSPL_DACR_MASK BIT(1)
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#define M98091_MIXSPL_DACL_MASK BIT(0)
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#define M98091_MIXSPL_MASK (63 << 0)
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/* M98091_REG_RIGHT_SPK_MIXER */
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#define M98091_SPK_SLAVE_MASK BIT(6)
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#define M98091_MIXSPR_MIC2_MASK BIT(5)
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#define M98091_MIXSPR_MIC1_MASK BIT(4)
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#define M98091_MIXSPR_LINEB_MASK BIT(3)
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#define M98091_MIXSPR_LINEA_MASK BIT(2)
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#define M98091_MIXSPR_DACR_MASK BIT(1)
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#define M98091_MIXSPR_DACL_MASK BIT(0)
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#define M98091_MIXSPR_MASK (63 << 0)
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/* M98091_REG_SPK_CONTROL */
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#define M98091_MIXSPRG_MASK (3 << 2)
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#define M98091_MIXSPLG_MASK (3 << 0)
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/* M98091_REG_LEFT_SPK_VOLUME */
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#define M98091_SPLM_MASK BIT(7)
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#define M98091_SPVOLL_MASK (63 << 0)
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/* M98091_REG_OUTPUT_ENABLE */
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#define M98091_HPREN_MASK BIT(7)
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#define M98091_HPLEN_MASK BIT(6)
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#define M98091_SPREN_MASK BIT(5)
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#define M98091_SPLEN_MASK BIT(4)
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#define M98091_RCVLEN_MASK BIT(3)
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#define M98091_RCVREN_MASK BIT(2)
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#define M98091_DAREN_MASK BIT(1)
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#define M98091_DALEN_MASK BIT(0)
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/* M98091_REG_DEVICE_SHUTDOWN */
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#define M98091_SHDNN_MASK BIT(7)
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#define M98091_DEFAULT_VOLUME 0x2A
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#define M98091_REVA 0x50
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#endif
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