1d07e565fc
Adds support for cooperative locking/unlocking the VPX vector registers. Provided that all VPX enabled threads use these routines to control access to the VPX vector registers, it will allow multiple threads to safely use them without the need for saving/restoring them upon each context switch. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
115 lines
9.7 KiB
ReStructuredText
115 lines
9.7 KiB
ReStructuredText
.. _hardware_arch_arc_support_status:
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Zephyr support status on ARC processors
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#######################################
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Overview
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********
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This page describes current state of Zephyr for ARC processors and some future
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plans. Please note that
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* plans are given without exact deadlines
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* software features require corresponding hardware to be present and
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configured the proper way
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* not all the features can be enabled at the same time
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Support status
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**************
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Legend:
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**Y** - yes, supported; **N** - no, not supported; **WIP** - Work In Progress;
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**TBD** - to be decided
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| | **Processor families** |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| | **EM** | **HS3x/4x** | **VPX** | **HS5x** | **HS6x** |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Port status | upstreamed | upstreamed | upstreamed [#f6]_ | upstreamed | upstreamed |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| **Features** |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | Y | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Hardware-assisted unaligned memory access | Y [#f2]_ | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Regular interrupts with multiple priority levels, direct interrupts | Y | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N | N |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Hardware floating point unit (FPU) | Y | Y | TBD [#f6]_ | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Hardware-assisted stack checking | Y | Y | Y | N | N |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Hardware-assisted atomic operations | N/A | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| DSP ISA | Y | N [#f3]_ | TBD [#f6]_ | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| DSP AGU/XY extensions | Y | N [#f3]_ | N/A | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Userspace | Y | Y | N | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Memory protection unit (MPU) | Y | Y | TBD | N | N |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Memory management unit (MMU) | N/A | N | TBD | N | N |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| SecureShield | Y | N/A | N/A | N/A | N/A |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| Single-thread kernel support [#f5]_ | Y | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| **Toolchains** |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| GNU (open source GCC-based) | Y | Y | N | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| MetaWare (proprietary Clang-based) | Y | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| **Simulators** |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| QEMU (open source) [#f4]_ | Y | Y | N | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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| nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
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Notes
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*****
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.. [#f1] usage of CCMs is limited on SMP systems
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.. [#f2] except the systems with secure features (SecureShield) due to HW
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limitation
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.. [#f3] We only support save/restore ACCL/ACCH registers in task's context.
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Rest of DSP/AGU registers save/restore isn't implemented but kernel
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itself does not use these registers. This allows single task per
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core to use DSP/AGU safely.
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.. [#f4] QEMU doesn't support all the ARC processor's HW features. For the
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detailed info please check the ARC QEMU documentation
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.. [#f5] Single-thread kernel is support only for single core targets
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.. [#f6] currently only ARC VPX scalar port is supported. The support of VPX vector pipeline, VCCM,
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STU is not included in this port, and require additional development and / or other runtime
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integration.
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VPX Vector Registers
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--------------------
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Zephyr supports a limited form sharing of the VPX vector registers known as
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cooperative sharing. Threads that use these registers must bookend the relevant
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sections with calls to :c:func:`arc_vpx_lock` and :c:func:`arc_vpx_unlock` to
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control access to this resource.
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.. note::
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If the system has multiple CPUs, then it is the responsibility of the
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application developer to both pin the thread to a single CPU before it
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attempts to get the cooperative lock, and not modify the CPU affinity
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while it is waiting for or holding that cooperative lock.
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Configuration Options
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=====================
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The cooperative sharing of the VPX vector registers is selected when
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configuration option :kconfig:option:`CONFIG_ARC_VPX_COOPERATIVE_SHARING`
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is enabled.
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