Daniel Leung 917bc51d2d xtensa: gdbstub: add arch_gdb_post_memory_write() ... This adds arch_gdb_post_memory_write() to deal with caching after GDB writing to memory. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2025-06-17 16:27:27 -05:00
..
offsets	xtensa: userspace: swap page tables via assembly code	2025-04-17 00:57:19 +02:00
startup
CMakeLists.txt	xtensa: update HAL path for custom compilations	2025-05-09 08:23:09 +02:00
coredump.c
cpu_idle.c
crt1.S
debug_helpers_asm.S
elf.c	llext: make unresolved symbol errors fatal	2025-06-17 16:09:50 +02:00
fatal.c
gdbstub.c	xtensa: gdbstub: add arch_gdb_post_memory_write()	2025-06-17 16:27:27 -05:00
gen_vectors.py
gen_zsr.py	xtensa: no need for flush register if threads are pin only	2025-04-17 00:57:19 +02:00
irq_manage.c
irq_offload.c
mem_manage.c
mmu.c	xtensa: userspace: pre-compute MMU registers at domain init	2025-04-17 00:57:19 +02:00
mpu.c
prep_c.c	xtensa: no need for flush register if threads are pin only	2025-04-17 00:57:19 +02:00
ptables.c	xtensa: allow flushing auto-refill DTLBs on page table swap	2025-05-28 20:01:58 +02:00
README_MMU.txt
README_WINDOWS.rst
smp.c
syscall_helper.c	xtensa: userspace: workaround return PC calc with loops	2025-04-17 00:57:19 +02:00
thread.c	xtensa: userspace: prevent potential privilege escalation	2025-04-17 00:57:19 +02:00
timing.c
tls.c
userspace.S	xtensa: allow flushing auto-refill DTLBs on page table swap	2025-05-28 20:01:58 +02:00
vector_handlers.c	xtensa: fix num_high_regs calculation when dumping stack	2025-06-17 16:27:27 -05:00
window_vectors.S
xcc_stubs.c
xtensa_asm2_util.S	xtensa: allow flushing auto-refill DTLBs on page table swap	2025-05-28 20:01:58 +02:00
xtensa_backtrace.c
xtensa_hifi.S
xtensa_intgen.py
xtensa_intgen.tmpl