fb7bdf0df4
This commit add require code for supporting RX architecture to Zephyr, it include: - Add require config and CMakelists for RX arch - Intialization startup code for RX - Interrupt and exception handling - Thread creation adn thread context switch - irq offload using SW interrupt Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
172 lines
3.9 KiB
ArmAsm
172 lines
3.9 KiB
ArmAsm
/*
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* Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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.list
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.section .text
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GTEXT(__start)
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__start :
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/* during initialization (before the main thread is started), z_initialization_process_stacks
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* is used to do the kernel initialization.
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*/
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mvtc #(_z_initialization_process_stacks + CONFIG_INITIALIZATION_STACK_SIZE),USP
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/* initialise interrupt stack pointer */
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mvtc #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE),ISP
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/* set exception vector address (_ExceptVectors is defined in vects.c) */
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#if CONFIG_HAS_EXCEPT_VECTOR_TABLE
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mvtc #_ExceptVectors, extb
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#endif
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/* set interrupt vector address (_rvectors_start is defined in vects.c) */
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mvtc #_rvectors_start, intb
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/* load data section from ROM to RAM */
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mov #_mdata,r2 /* src ROM address of data section in R2 */
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mov #_data,r1 /* dest start RAM address of data section in R1 */
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mov #_edata,r3 /* end RAM address of data section in R3 */
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sub r1,r3 /* size of data section in R3 (R3=R3-R1) */
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#ifdef __RX_ALLOW_STRING_INSNS__
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smovf /* block copy R3 bytes from R2 to R1 */
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#else
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cmp #0, r3
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beq 2f
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1: mov.b [r2+], r5
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mov.b r5, [r1+]
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sub #1, r3
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bne 1b
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2:
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#endif
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/* bss initialisation: zero out bss */
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mov #0,r2 /* load R2 reg with zero */
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mov #_ebss, r3 /* store the end address of bss in R3 */
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mov #_bss, r1 /* store the start address of bss in R1 */
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sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */
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sstr.b
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#ifdef CONFIG_INIT_STACKS
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/* initialize the irq stack (it is located in the bss section) */
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mov #0xaa,r2 /* initialization value 0xaa */
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mov #_z_interrupt_stacks, r1 /* start address */
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mov #CONFIG_ISR_STACK_SIZE, r3 /* stack size */
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sstr.b
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#endif
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/* setup PSW - use user stack register and lock interrupts during initialization */
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mvtc #0x20000, psw
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#ifdef CPPAPP
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bsr __rx_init
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#endif
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/* start user program */
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bsr _z_cstart
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bsr _exit
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#ifdef CPPAPP
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.global _rx_run_preinit_array
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.type _rx_run_preinit_array,@function
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_rx_run_preinit_array:
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mov #__preinit_array_start,r1
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mov #__preinit_array_end,r2
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mov #_rx_run_inilist,r7
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jsr r7
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.global _rx_run_init_array
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.type _rx_run_init_array,@function
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_rx_run_init_array:
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mov #__init_array_start,r1
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mov #__init_array_end,r2
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mov #4, r3
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mov #_rx_run_inilist,r7
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jsr r7
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.global _rx_run_fini_array
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.type _rx_run_fini_array,@function
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_rx_run_fini_array:
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mov #__fini_array_start,r2
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mov #__fini_array_end,r1
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mov #-4, r3
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/* fall through */
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_rx_run_inilist:
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next_inilist:
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cmp r1,r2
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beq.b done_inilist
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mov.l [r1],r4
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cmp #-1, r4
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beq.b skip_inilist
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cmp #0, r4
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beq.b skip_inilist
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pushm r1-r3
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jsr r4
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popm r1-r3
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skip_inilist:
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add r3,r1
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mov #next_inilist,r7
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jsr r7
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done_inilist:
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rts
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.section .init,"ax"
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.balign 4
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.global __rx_init
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__rx_init:
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.section .fini,"ax"
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.balign 4
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.global __rx_fini
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__rx_fini:
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mov #_rx_run_fini_array,r7
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jsr r7
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.section .sdata
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.balign 4
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.global __gp
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.weak __gp
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__gp:
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.section .data
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.global ___dso_handle
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.weak ___dso_handle
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___dso_handle:
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.long 0
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.section .init,"ax"
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mov #_rx_run_preinit_array,r7
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jsr r7
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mov #_rx_run_init_array,r7
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jsr r7
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rts
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.global __rx_init_end
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__rx_init_end:
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.section .fini,"ax"
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rts
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.global __rx_fini_end
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__rx_fini_end:
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#endif
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/* call to exit*/
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_exit:
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bra _loop_here
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_loop_here:
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bra _loop_here
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.text
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.end
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