fb7bdf0df4
This commit add require code for supporting RX architecture to Zephyr, it include: - Add require config and CMakelists for RX arch - Intialization startup code for RX - Interrupt and exception handling - Thread creation adn thread context switch - irq offload using SW interrupt Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
75 lines
1.4 KiB
Plaintext
75 lines
1.4 KiB
Plaintext
# Renesas RX architecture configuration options
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# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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menu "Renesas RX Options"
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depends on RX
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config ARCH
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string
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default "rx"
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config CPU_RXV1
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bool
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help
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Set if the processor supports the Renesas RXv1 instruction set.
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config CPU_RXV2
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bool
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help
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Set if the processor supports the Renesas RXv2 instruction set.
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config CPU_RXV3
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bool
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help
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Set if the processor supports the Renesas RXv3 instruction set.
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config HAS_EXCEPT_VECTOR_TABLE
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bool
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help
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Set if the processor has the exception vector table.
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config XIP
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default y
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config NUM_IRQ_PRIO_LEVELS
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int "Number of supported interrupt priority levels"
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range 1 16
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default 16
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help
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Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The
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minimum value is 1. The BSP must provide a valid default for proper
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operation.
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config NUM_IRQS
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int
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default 256
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config GEN_ISR_TABLES
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default y
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config GEN_SW_ISR_TABLE
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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config GEN_IRQ_START_VECTOR
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default 16
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config DYNAMIC_INTERRUPTS
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default y
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config MAIN_STACK_SIZE
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default 1024
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config INITIALIZATION_STACK_SIZE
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int "Initialization stack size (in bytes)"
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default 512
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help
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Stack size for initialization process of kernel (in bytes)
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endmenu
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