8bd4f244b0
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
170 lines
5.0 KiB
C
170 lines
5.0 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Kernel fatal error handler for ARM Cortex-M and Cortex-R
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*
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* This module provides the z_arm_fatal_error() routine for ARM Cortex-M
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* and Cortex-R CPUs.
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*/
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#include <zephyr/kernel.h>
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#include <kernel_arch_data.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
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#ifdef CONFIG_EXCEPTION_DEBUG
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static void esf_dump(const struct arch_esf *esf)
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{
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LOG_ERR("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x",
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esf->basic.a1, esf->basic.a2, esf->basic.a3);
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LOG_ERR("r3/a4: 0x%08x r12/ip: 0x%08x r14/lr: 0x%08x",
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esf->basic.a4, esf->basic.ip, esf->basic.lr);
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LOG_ERR(" xpsr: 0x%08x", esf->basic.xpsr);
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) {
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LOG_ERR("s[%2d]: 0x%08x s[%2d]: 0x%08x"
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" s[%2d]: 0x%08x s[%2d]: 0x%08x",
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i, (uint32_t)esf->fpu.s[i],
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i + 1, (uint32_t)esf->fpu.s[i + 1],
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i + 2, (uint32_t)esf->fpu.s[i + 2],
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i + 3, (uint32_t)esf->fpu.s[i + 3]);
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}
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#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
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for (int i = 0; i < ARRAY_SIZE(esf->fpu.d); i += 4) {
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LOG_ERR("d[%2d]: 0x%16llx d[%2d]: 0x%16llx"
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" d[%2d]: 0x%16llx d[%2d]: 0x%16llx",
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i, (uint64_t)esf->fpu.d[i],
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i + 1, (uint64_t)esf->fpu.d[i + 1],
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i + 2, (uint64_t)esf->fpu.d[i + 2],
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i + 3, (uint64_t)esf->fpu.d[i + 3]);
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}
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#endif
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LOG_ERR("fpscr: 0x%08x", esf->fpu.fpscr);
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#endif
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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const struct _callee_saved *callee = esf->extra_info.callee;
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if (callee != NULL) {
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LOG_ERR("r4/v1: 0x%08x r5/v2: 0x%08x r6/v3: 0x%08x",
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callee->v1, callee->v2, callee->v3);
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LOG_ERR("r7/v4: 0x%08x r8/v5: 0x%08x r9/v6: 0x%08x",
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callee->v4, callee->v5, callee->v6);
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LOG_ERR("r10/v7: 0x%08x r11/v8: 0x%08x psp: 0x%08x",
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callee->v7, callee->v8, callee->psp);
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}
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LOG_ERR("EXC_RETURN: 0x%0x", esf->extra_info.exc_return);
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
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esf->basic.pc);
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}
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#endif /* CONFIG_EXCEPTION_DEBUG */
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void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf)
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{
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#ifdef CONFIG_EXCEPTION_DEBUG
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if (esf != NULL) {
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esf_dump(esf);
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}
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#endif /* CONFIG_EXCEPTION_DEBUG */
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/* LOG the IRQn that was unhandled */
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#if defined(CONFIG_CPU_CORTEX_M)
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if (reason == K_ERR_SPURIOUS_IRQ) {
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uint32_t irqn = __get_IPSR() - 16;
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LOG_ERR("Unhandled IRQn: %d", irqn);
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}
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#endif
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z_fatal_error(reason, esf);
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}
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/**
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* @brief Handle a software-generated fatal exception
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* (e.g. kernel oops, panic, etc.).
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*
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* Notes:
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* - the function is invoked in SVC Handler
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* - if triggered from nPRIV mode, only oops and stack fail error reasons
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* may be propagated to the fault handling process.
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* - We expect the supplied exception stack frame to always be a valid
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* frame. That is because, if the ESF cannot be stacked during an SVC,
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* a processor fault (e.g. stacking error) will be generated, and the
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* fault handler will executed instead of the SVC.
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*
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* @param esf exception frame
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* @param callee_regs Callee-saved registers (R4-R11)
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* @param exc_return EXC_RETURN value present in LR after exception entry.
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*/
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void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs, uint32_t exc_return)
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{
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#if !(defined(CONFIG_EXTRA_EXCEPTION_INFO) && defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE))
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ARG_UNUSED(callee_regs);
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#endif
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/* Stacked R0 holds the exception reason. */
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unsigned int reason = esf->basic.r0;
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z_arm_set_fault_sp(esf, exc_return);
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#if defined(CONFIG_USERSPACE)
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if (z_arm_preempted_thread_in_user_mode(esf)) {
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/*
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* Exception triggered from user mode.
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*
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* User mode is only allowed to induce oopses and stack check
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* failures via software-triggered system fatal exceptions.
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*/
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if (!((esf->basic.r0 == K_ERR_KERNEL_OOPS) ||
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(esf->basic.r0 == K_ERR_STACK_CHK_FAIL))) {
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reason = K_ERR_KERNEL_OOPS;
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}
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}
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#endif /* CONFIG_USERSPACE */
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#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
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z_arm_fatal_error(reason, esf);
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#else
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struct arch_esf esf_copy;
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memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info));
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#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* extra exception info is collected in callee_reg param
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* on CONFIG_ARMV7_M_ARMV8_M_MAINLINE
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*/
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esf_copy.extra_info = (struct __extra_esf_info) {
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.callee = callee_regs,
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};
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#else
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/* extra exception info is not collected for kernel oops
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* path today so we make a copy of the ESF and zero out
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* that information
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*/
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esf_copy.extra_info = (struct __extra_esf_info) { 0 };
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#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
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z_arm_fatal_error(reason, &esf_copy);
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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}
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FUNC_NORETURN void arch_syscall_oops(void *ssf_ptr)
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{
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uint32_t *ssf_contents = ssf_ptr;
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struct arch_esf oops_esf = { 0 };
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/* TODO: Copy the rest of the register set out of ssf_ptr */
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oops_esf.basic.pc = ssf_contents[3];
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z_arm_fatal_error(K_ERR_KERNEL_OOPS, &oops_esf);
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CODE_UNREACHABLE;
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}
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