4796746b5e
This make MCUboot build as Zephyr application. Providing optinal 2nd stage bootloader to the IDF bootloader, which is used by default. This provides more flexibility when building and loading multiple images and aims to brings better DX to users by using the sysbuild. MCUboot and applications has now separate linker scripts. Signed-off-by: Marek Matej <marek.matej@espressif.com>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc.h"
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/*
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* Instruction Cache definitions
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*/
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#if defined(CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB)
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#define ESP32S3_ICACHE_SIZE ICACHE_SIZE_16KB
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#else
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#define ESP32S3_ICACHE_SIZE ICACHE_SIZE_32KB
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#endif
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#if defined(CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B)
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#define ESP32S3_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#else
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#define ESP32S3_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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/*
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* Data Cache definitions
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*/
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#if defined(CONFIG_ESP32S3_DATA_CACHE_16KB) || defined(CONFIG_ESP32S3_DATA_CACHE_32KB)
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#define ESP32S3_DCACHE_SIZE DCACHE_SIZE_32KB
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#else
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#define ESP32S3_DCACHE_SIZE DCACHE_SIZE_64KB
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#endif
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#if defined(CONFIG_ESP32S3_DATA_CACHE_LINE_16B)
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#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#elif defined(CONFIG_ESP32S3_DATA_CACHE_LINE_32B)
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#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#else
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#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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#define CACHE_MEMORY_ICACHE_LOW CACHE_ICACHE0
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#ifndef CONFIG_MCUBOOT
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extern void Cache_Enable_ICache(uint32_t autoload);
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void IRAM_ATTR esp_config_instruction_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
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Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_HALF;
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#else
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Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1);
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cache_size = CACHE_SIZE_FULL;
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#endif
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS
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cache_ways = CACHE_4WAYS_ASSOC;
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#else
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cache_ways = CACHE_8WAYS_ASSOC;
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#endif
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B
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cache_line_size = CACHE_LINE_SIZE_32B;
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#else
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cache_line_size = CACHE_LINE_SIZE_64B;
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#endif
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Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_ICache_All();
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Cache_Enable_ICache(0);
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}
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void IRAM_ATTR esp_config_data_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S3_DATA_CACHE_32KB
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Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK1, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_HALF;
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#else
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Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1);
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cache_size = CACHE_SIZE_FULL;
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#endif
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#if CONFIG_ESP32S3_DATA_CACHE_4WAYS
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cache_ways = CACHE_4WAYS_ASSOC;
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#else
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cache_ways = CACHE_8WAYS_ASSOC;
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#endif
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#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B
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cache_line_size = CACHE_LINE_SIZE_32B;
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#else
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cache_line_size = CACHE_LINE_SIZE_64B;
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#endif
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Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_DCache_All();
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}
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#endif /* CONFIG_MCUBOOT */
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