32bb2395c2
Kernel timeouts have always been a 32 bit integer despite the existence of generation macros, and existing code has been inconsistent about using them. Upcoming commits are going to make the timeout arguments opaque, so fix things up to be rigorously correct. Changes include: + Adding a K_TIMEOUT_EQ() macro for code that needs to compare timeout values for equality (e.g. with K_FOREVER or K_NO_WAIT). + Adding a k_msleep() synonym for k_sleep() which can continue to take integral arguments as k_sleep() moves away to timeout arguments. + Pervasively using the K_MSEC(), K_SECONDS(), et. al. macros to generate timeout arguments. + Removing the usage of K_NO_WAIT as the final argument to K_THREAD_DEFINE(). This is just a count of milliseconds and we need to use a zero. This patch include no logic changes and should not affect generated code at all. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef INTERRUPT_UTIL_H_
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#define INTERRUPT_UTIL_H_
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#include <ztest.h>
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#define MS_TO_US(ms) (ms * USEC_PER_MSEC)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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static inline u32_t get_available_nvic_line(u32_t initial_offset)
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{
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int i;
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for (i = initial_offset - 1; i >= 0; i--) {
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if (NVIC_GetEnableIRQ(i) == 0) {
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/*
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* Interrupts configured statically with IRQ_CONNECT(.)
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* are automatically enabled. NVIC_GetEnableIRQ()
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* returning false, here, implies that the IRQ line is
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* either not implemented or it is not enabled, thus,
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* currently not in use by Zephyr.
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*/
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/* Set the NVIC line to pending. */
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NVIC_SetPendingIRQ(i);
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if (NVIC_GetPendingIRQ(i)) {
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/*
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* If the NVIC line is pending, it is
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* guaranteed that it is implemented; clear the
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* line and return the NVIC line number.
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*/
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NVIC_ClearPendingIRQ(i);
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break;
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}
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}
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}
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zassert_true(i >= 0, "No available IRQ line\n");
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return i;
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}
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
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|| defined(CONFIG_CPU_CORTEX_M0PLUS)
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NVIC_SetPendingIRQ(irq);
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#else
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_GIC)
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#include <drivers/interrupt_controller/gic.h>
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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/* Ensure that the specified IRQ number is a valid SGI interrupt ID */
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zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq);
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/*
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* Generate a software generated interrupt and forward it to the
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* requesting CPU.
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*/
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sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
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GICD_SGIR);
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}
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#elif defined(CONFIG_CPU_ARCV2)
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
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}
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#else
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/* for not supported architecture */
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#define NO_TRIGGER_FROM_SW
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#endif
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#endif /* INTERRUPT_UTIL_H_ */
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