df41deac1c
It doesn't make sense to keep the aarch32 directory in the
'arch/arm/core' directory as the aarch64 has been moved out.
This commit introduces the following major changes.
1. Move all directories and files in 'arch/arm/core/aarch32' to
'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory.
2. Move all directories and files in 'arch/include/aarch32' to
'arch/include' and remove the 'arch/include/aarch32' directory.
3. Remove the nested including in the 'arch/include/kernel_arch_func.h'
and 'arch/include/offsets_short_arch.h' header files.
4. Change the path string which is influenced by the changement 1
and 2.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Stack helpers for Cortex-M CPUs
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*
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* Stack helper functions.
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*/
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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#include <cmsis_core.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS,
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CONFIG_ISR_STACK_SIZE);
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/**
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*
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* @brief Setup interrupt stack
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*
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* On Cortex-M, the interrupt stack is registered in the MSP (main stack
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* pointer) register, and switched to automatically when taking an exception.
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*
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*/
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static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
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{
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uint32_t msp =
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(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
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K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]);
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__set_MSP(msp);
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#if defined(CONFIG_BUILTIN_STACK_GUARD)
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#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
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__set_MSPLIM((uint32_t)z_interrupt_stacks[0]);
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#else
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#error "Built-in MSP limit checks not supported by HW"
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#endif
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#endif /* CONFIG_BUILTIN_STACK_GUARD */
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#if defined(CONFIG_STACK_ALIGN_DOUBLE_WORD)
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/* Enforce double-word stack alignment on exception entry
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* for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
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* of ARM Cortex-M processors this setting is enforced by
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* default and it is not configurable.
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*/
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#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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#endif
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#endif /* CONFIG_STACK_ALIGN_DOUBLE_WORD */
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ */
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