Kevin Wang d97dcd3e09 dts: riscv: andes: andes_v5_ae350: added CPU number to 8 hart ... Add cpu node for supporting 8 cores. Signed-off-by: Kevin Wang <yunkai@andestech.com>		2022-08-03 05:00:14 +01:00
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andes	dts: riscv: andes: andes_v5_ae350: added CPU number to 8 hart	2022-08-03 05:00:14 +01:00
espressif	esp32: dts: add RTC timer node	2022-07-27 09:48:33 +02:00
gigadevice	dts: arm: gigadevice: Add DMA configuration	2022-08-02 09:13:21 +02:00
ite	dts: riscv: Remove label property from devicetrees	2022-07-26 12:57:23 -05:00
microsemi	dts: riscv: microsemi-miv: define CLINT	2022-08-02 09:12:31 +02:00
openisa	dts: riscv: Remove label property from devicetrees	2022-07-26 12:57:23 -05:00
sifive	dts: riscv: sifive: use sifive,clint0	2022-08-02 09:12:31 +02:00
starfive	dts: riscv: starfive: align clint description with Linux	2022-08-02 09:12:31 +02:00
telink	dts: riscv: telink: add DT entry for machine timer	2022-08-02 09:12:31 +02:00
mpfs-icicle.dtsi	include: add missing zephyr/ prefixes	2022-08-02 18:03:58 +01:00
neorv32.dtsi	dts: riscv: neorv32: define machine timer	2022-08-02 09:12:31 +02:00
riscv32-litex-vexriscv.dtsi	dts: riscv: Remove label property from devicetrees	2022-07-26 12:57:23 -05:00
virt.dtsi	dts: riscv: virt: use sifive,clint0	2022-08-02 09:12:31 +02:00