zephyr/dts/bindings/cpu/cpu.yaml
Kumar Gala f8b7aabd12 dts: bindings: Remove defaults for cache lines from cpu binding
The default values for i/d-cache line size doesnt make sense.  These
shouldn't use defaults.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-03 13:41:47 -05:00

25 lines
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YAML

# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Common fields for CPUs
include: base.yaml
properties:
clock-frequency:
type: int
required: false
description: Clock frequency in Hz
cpu-power-states:
type: phandles
required: false
description: List of power management states supported by this cpu
i-cache-line-size:
type: int
required: false
description: i-cache line size
d-cache-line-size:
type: int
required: false
description: d-cache line size