799f37b421
In some drivers, noncache memory need to be used for dma coherent
memroy, so add nocache memory segment mapping and support for ARM64
platforms.
The following variables definition example shows they will use nocache
memory allocation:
int var1 __nocache;
int var2 __attribute__((__section__(".nocache")));
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
29 lines
604 B
Plaintext
29 lines
604 B
Plaintext
/*
|
|
* Copyright (c) 2019 Nordic Semiconductor ASA
|
|
* Copyright (c) 2019 Intel Corporation
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/* Copied from linker.ld */
|
|
|
|
/* Non-cached region of RAM */
|
|
SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
|
|
{
|
|
#if defined(CONFIG_MMU)
|
|
MMU_ALIGN;
|
|
#else
|
|
MPU_ALIGN(_nocache_ram_size);
|
|
#endif
|
|
_nocache_ram_start = .;
|
|
*(.nocache)
|
|
*(".nocache.*")
|
|
#if defined(CONFIG_MMU)
|
|
MMU_ALIGN;
|
|
#else
|
|
MPU_ALIGN(_nocache_ram_size);
|
|
#endif
|
|
_nocache_ram_end = .;
|
|
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
|
_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;
|