70c403c215
An initial implementation for memory management using the ARMv7 MMU. A single L1 translation table for the whole 4 GB address space is al- ways present, a configurable number of L2 page tables are linked to the L1 table based on the static memory area configuration at boot time, or whenever arch_mem_map/arch_mem_unmap are called at run-time. Currently, a CPU with the Multiprocessor Extensions and execution at PL1 are always assumed. Userspace-related features or thread stack guard pages are not yet supported. Neither are LPAE, PXN or TEX re- mapping. All mappings are currently assigned to the same domain. Re- garding the permissions model, access permissions are specified using the AP[2:1] model rather than the older AP[2:0] model, which, accor- ding to ARM's documentation, is deprecated and should no longer be used. The newer model adds some complexity when it comes to mapping pages as unaccessible (the AP[2:1] model doesn't support explicit specification of "no R, no W" permissions, it's always at least "RO"), this is accomplished by invalidating the ID bits of the respective page's PTE. Includes sources, Kconfig integration, adjusted CMakeLists and the modified linker command file (proper section alignment!). Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/*
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* Copyright (c) 2013-2016 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Private kernel definitions (ARM)
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*
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* This file contains private kernel function definitions and various
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* other definitions for the 32-bit ARM Cortex-A/R/M processor architecture
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* family.
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*
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* This file is also included by assembly language files which must #define
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* _ASMLANGUAGE before including this header file. Note that kernel
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* assembly source files obtains structure offset values via "absolute symbols"
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* in the offsets.o module.
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*/
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_
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#include <kernel_arch_data.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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extern void z_arm_fault_init(void);
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extern void z_arm_cpu_idle_init(void);
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#ifdef CONFIG_ARM_MPU
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extern void z_arm_configure_static_mpu_regions(void);
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extern void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread);
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extern int z_arm_mpu_init(void);
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#endif /* CONFIG_ARM_MPU */
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#ifdef CONFIG_ARM_AARCH32_MMU
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extern int z_arm_mmu_init(void);
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#endif /* CONFIG_ARM_AARCH32_MMU */
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static ALWAYS_INLINE void arch_kernel_init(void)
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{
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z_arm_interrupt_stack_setup();
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z_arm_exc_setup();
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z_arm_fault_init();
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z_arm_cpu_idle_init();
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z_arm_clear_faults();
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#if defined(CONFIG_ARM_MPU)
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z_arm_mpu_init();
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/* Configure static memory map. This will program MPU regions,
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* to set up access permissions for fixed memory sections, such
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* as Application Memory or No-Cacheable SRAM area.
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*
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* This function is invoked once, upon system initialization.
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*/
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z_arm_configure_static_mpu_regions();
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#endif /* CONFIG_ARM_MPU */
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#if defined(CONFIG_ARM_AARCH32_MMU)
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z_arm_mmu_init();
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#endif /* CONFIG_ARM_AARCH32_MMU */
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}
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static ALWAYS_INLINE void
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arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
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{
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thread->arch.swap_return_value = value;
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}
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#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)
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extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
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k_thread_entry_t main_func,
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void *p1, void *p2, void *p3);
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#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \
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z_arm_switch_to_main_no_multithreading
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#endif /* !CONFIG_MULTITHREADING && CONFIG_CPU_CORTEX_M */
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extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry,
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void *p1, void *p2, void *p3,
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uint32_t stack_end,
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uint32_t stack_start);
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extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_ */
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