ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
70 lines
2.0 KiB
C
70 lines
2.0 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef MVIC_H
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#define MVIC_H
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#include <arch/cpu.h>
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/* Register defines. A lot of similarities to APIC, but not quite the same */
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#define MVIC_TPR 0xFEE00080 /* Task priority register */
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#define MVIC_PPR 0xFEE000A0 /* Process priority register */
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#define MVIC_EOI 0xFEE000B0 /* End-of-interrupt register */
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#define MVIC_SIVR 0xFEE000F0 /* Spurious interrupt vector register */
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#define MVIC_ISR 0xFEE00110 /* In-service register */
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#define MVIC_IRR 0xFEE00210 /* Interrupt request register */
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#define MVIC_LVTTIMER 0xFEE00320 /* Local vector table timer register */
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#define MVIC_ICR 0xFEE00380 /* Timer initial count register */
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#define MVIC_CCR 0xFEE00390 /* Timer current count register */
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#define MVIC_IOREGSEL 0xFEC00000 /* Register select (index) */
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#define MVIC_IOWIN 0xFEC00010 /* Register windows (data) */
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/* MVIC_LVTTIMER bits */
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#define MVIC_LVTTIMER_MASK BIT(16)
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#define MVIC_LVTTIMER_PERIODIC BIT(17)
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/* MVIC_IOWIN bits */
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#define MVIC_IOWIN_TRIGGER_LEVEL BIT(15)
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#define MVIC_IOWIN_TRIGGER_EDGE 0
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#define MVIC_IOWIN_MASK BIT(16)
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#define MVIC_IOWIN_SUPPORTED_BITS_MASK (MVIC_IOWIN_MASK | \
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MVIC_IOWIN_TRIGGER_LEVEL)
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/* MVIC IOREGSEL register usage defines */
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#define MVIC_LOW_NIBBLE_MASK 0x07
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#define MVIC_HIGH_NIBBLE_MASK 0x18
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#define MVIC_NUM_RTES 32
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#define _IRQ_TRIGGER_EDGE MVIC_IOWIN_TRIGGER_EDGE
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#define _IRQ_TRIGGER_LEVEL MVIC_IOWIN_TRIGGER_LEVEL
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/* MVIC does not support IRQ_POLARITY_HIGH or IRQ_POLARITY_LOW,
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* leave undefined
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*/
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#ifndef _ASMLANGUAGE
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/* Implementation of irq_controller.h interface */
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#define __IRQ_CONTROLLER_VECTOR_MAPPING(irq) ((irq) + 32)
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void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
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uint32_t flags);
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int __irq_controller_isr_vector_get(void);
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#else /* _ASMLANGUAGE */
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.macro __irq_controller_eoi
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xorl %eax, %eax /* zeroes eax */
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movl %eax, MVIC_EOI /* tell MVIC the IRQ is handled */
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.endm
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#endif
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#endif /* MVIC_H */
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