ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
74 lines
1.7 KiB
Plaintext
74 lines
1.7 KiB
Plaintext
# Kconfig.dw - DesignWare SPI driver configuration options
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#
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#
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# Copyright (c) 2015-2016 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig SPI_DW
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bool
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prompt "Designware SPI controller driver"
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depends on SPI
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default n
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help
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Enable support for Designware's SPI controllers.
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if SPI_DW
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config SPI_DW_ARC_AUX_REGS
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bool "Registers are part of ARC auxiliary registers"
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depends on SPI_DW && ARC
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default y
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help
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SPI IP block registers are part of user extended auxiliary
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registers and thus their access is different than memory
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mapped registers.
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choice
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depends on SPI_DW
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prompt "DesignWare SPI interrupt management logic"
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default SPI_DW_INTERRUPT_SINGLE_LINE
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config SPI_DW_INTERRUPT_SINGLE_LINE
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bool "Single interrupt line for all interrupts"
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help
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Only one line is used to trigger interrupts: RX, TX and ERROR
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interrupt go all through that line, undifferentiated.
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config SPI_DW_INTERRUPT_SEPARATED_LINES
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bool "One line per-interrupt type (RX, TX and ERROR)"
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help
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Each interrupt gets a dedicated line
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endchoice
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config SPI_DW_CLOCK_GATE
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bool "Enable glock gating"
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depends on SPI_DW && SOC_QUARK_SE_C1000
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select CLOCK_CONTROL
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default n
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config SPI_DW_CLOCK_GATE_DRV_NAME
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string
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depends on SPI_DW_CLOCK_GATE
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default ""
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config SPI_DW_FIFO_DEPTH
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int "Rx and Tx FIFO Depth"
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help
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Corresponds to the SSI_TX_FIFO_DEPTH and
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SSI_RX_FIFO_DEPTH of the DesignWare Syncrhonous
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Serial Interface. Depth ranges from 2-256.
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config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on SPI_DW_CLOCK_GATE
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config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on SPI_DW_CLOCK_GATE
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endif # SPI_DW
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