Tom Burdick 1e9ada4eb9 dma: cavs: Add gpdma derivative of dw dma for cavs ... Intel's adsp needs to set, at a minimum, a clocking bit before the driver can initialize the designware dma controller. In many ways it is the designware dmac IP but with additional registers and functionality added on top of it. So the code structure here follows how the hardware appears to be designed, layered on top of the designware driver. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>		2022-02-21 20:59:08 -05:00
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intel_byt_adsp.dtsi	dts: use 'cdns,' instead of 'cadence,' consistently	2021-08-17 17:51:57 -04:00
intel_cavs15.dtsi	soc/intel_adsp_cavs15: Use new IDC driver	2021-12-07 12:09:02 -05:00
intel_cavs18.dtsi	soc/intel_adsp: Correct LP-SRAM sizes in DTS	2021-12-14 18:43:05 -06:00
intel_cavs20.dtsi	soc/intel_adsp: Correct LP-SRAM sizes in DTS	2021-12-14 18:43:05 -06:00
intel_cavs25.dtsi	dma: cavs: Add gpdma derivative of dw dma for cavs	2022-02-21 20:59:08 -05:00
intel_s1000.dtsi	soc/intel_s1000: Add new cAVS shim & IDC interfaces	2021-12-07 12:06:21 -05:00