Tomasz Bursztyka 4047b793c8 drivers/interrupt_controller: Generate proper MSI address on VT-D ... SHV bit depends on the number of vectors allocated. If it's facing a multi-vector MSI array, it will set the bit. If not the bit must be 0. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>		2022-01-07 10:47:27 -05:00
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exti_stm32.h
gd32_exti.h	drivers: interrupt_controller: initial support for GD32 EXTI	2022-01-04 20:49:00 -05:00
gic.h	interrupt_controller: gicv3: add support for LPIs	2021-09-28 19:45:29 -04:00
gicv3_its.h	interrupt_controller: Add GICv3 ITS API	2021-09-28 19:45:29 -04:00
intc_esp32.h	esp32: drivers: interrupt_controller: add interrupt allocation support	2021-07-16 07:19:28 -04:00
intc_esp32c3.h	interrupt-controller: intc_esp32c3: make logs optional	2021-10-02 14:33:24 -04:00
intc_mchp_xec_ecia.h	Microchip: MEC172x: eSPI driver	2021-10-26 09:27:20 -04:00
intel_vtd.h	drivers/interrupt_controller: Generate proper MSI address on VT-D	2022-01-07 10:47:27 -05:00
ioapic.h
loapic.h	interrupt_controller: loapic: remove duplicate identifier	2021-04-29 21:09:54 -04:00
sam0_eic.h
sysapic.h