Scott Worley af67564573 soc: mchp: Update 32KHz programming sequence ... Based upon discussions with HW designers the 32KHz programming sequence can be simplified. When FW writes a value to the VBAT 32KHz Clock Enable register HW checks if the value is the same as the current value. If the same the HW does nothing. If different HW begins a sequence to switch off the current 32KHz source, revert to ring oscillator, and switch to the new source. FW should program the new value and then spin until the PCR OSC ID PLL Lock bit goes to 1. Signed-off-by: Scott Worley <scott.worley@microchip.com>		2021-01-27 21:37:39 -05:00
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arc	ARC: soc: hsdk: add MWDT compiler options	2021-01-26 06:18:02 -05:00
arm	soc: mchp: Update 32KHz programming sequence	2021-01-27 21:37:39 -05:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	soc/riscv: add the QEMU "RISC-V VirtIO board"	2021-01-15 13:06:33 -05:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	x86: reserve the first megabyte	2021-01-23 19:47:23 -05:00
xtensa	soc/esp32: Move full logging library to IRAM	2021-01-23 08:43:10 -05:00
Kconfig	timing: introduce timing functions as a generic feature	2020-09-05 13:28:38 -05:00