Nicolas Pitre 3f8e326d1a riscv: stop preserving the tp register needlessly ... The tp (x4) register is neither caller nor callee saved according to the RISC-V standard calling convention. It only has to be set on thread context switching and is otherwise read-only. To protect the kernel against a possible rogue user thread, the tp is also re-set on exception entry from u-mode. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2022-06-23 13:12:05 -04:00
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zephyr	riscv: stop preserving the tp register needlessly	2022-06-23 13:12:05 -04:00