Georgij Cernysiov 8a4b078c85 include: drivers: clock_control: stm32: fix xtpre ... Correct DT property to set correct STM32_PLL_XTPRE value. The driver bindings defined `xtpre` instead of used `xtre` in the `DT_PROP` macro. That allows to use F1 PLL clock with division by 2. Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>		2022-02-08 10:20:53 -05:00
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arm_clock_control.h
clock_agilex_ll.h	drivers: clock_control: Add clock driver for Intel SoC FPGA Agilex	2021-10-12 08:37:03 -04:00
clock_control_litex.h	drivers: clock_control_litex: remove MMCM_NAME	2021-08-19 17:20:21 -04:00
lpc11u6x_clock_control.h
mchp_xec_clock_control.h	Microchip: MEC172x clock control driver	2021-07-21 17:46:07 -04:00
nrf_clock_control.h	drivers: clock_control: nrf: fix cpp compatibility	2021-09-14 09:56:46 +02:00
rcar_clock_control.h	drivers: clock_control: add R-Car CPG MSSR driver	2021-04-22 10:38:45 +02:00
stm32_clock_control.h	include: drivers: clock_control: stm32: fix xtpre	2022-02-08 10:20:53 -05:00