Francisco Munoz 950679470d soc: microchip_mec: mec1501 Add pinmux definitions ... Define pinmux base addresses from gpio bases. Pinmux and gpio functionality are located in the same PCR register for each pin. Introduce pinmux Kconfig switches for the SOC. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>		2019-05-27 09:24:08 -04:00
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arc	qmsi: set type to boolean when selecting QMSI	2019-05-24 15:10:16 -04:00
arm	soc: microchip_mec: mec1501 Add pinmux definitions	2019-05-27 09:24:08 -04:00
nios2	uart/ns16550, drivers/pcie: add PCI(e) support	2019-04-17 10:50:05 -07:00
posix	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
riscv32	linker: Port usage of custom-sections to use Cmake	2019-05-20 22:28:28 -04:00
x86	qmsi: set type to boolean when selecting QMSI	2019-05-24 15:10:16 -04:00
x86_64/x86_64	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
xtensa	soc: intel_s1000: change cached regions to write-through	2019-04-12 17:59:06 -04:00
Kconfig	soc: Port usage of soc-*.ld to use Cmake	2019-05-20 22:28:28 -04:00