d68c18471e
The CH32V006 is part of the CH32V00x series of 32 bit RISC-V microcontrollers. This series is an evolution of the CH32V003 which was used as a basis for this Devicetree definition. Compared to the CH32V003, thie CH32V006 has an extra GPIO port (PB), an extra UART (UART2), 8 KiB of RAM, 62 KiB of flash, and uses the QingKe V2C core. Signed-off-by: Michael Hope <michaelh@juju.nz> |
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| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| rx/renesas | ||
| sparc/gaisler | ||
| vendor | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||