This adds an architecture-specific post processing after memory
writes. This introduction is due to GDB's behavior regarding
breakpoints in code. GDB may choose to write break instructions
instead of using hardware breakpoints to interrupt code
execution (e.g. for manual breakpoint or stepping through code).
There is no separate GDB packet type for this. So we need to
make an assumption that a memory write may be to setup break
instructions. Different architectures may have their own unique
ways of dealing with instruction cache in this situation. So we
defer to the architecture code to handle this.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
3fbd7dfb75