zephyr/dts/arm
Trond Einar Snekvik b613c2350e dts: nordic: Set default binding for all multi mode buses
As Nordic SPI, I2C and UART buses can act as both slave and master,
these nodes can have different compatible properties, and are annotated
with a comment, instead of a compatible property. This forces boards to
put compatible properties in their definitions, which is unnecessary
boilerplate for most boards, as most boards acts as masters on these
buses.

Set master mode by default for these buses, to reduce boilerplate and
potential errors in board definitions. Boards that need to act as slave
nodes will just continue to override the compatible properties.
Likewise, existing boards that override this compatible property with a
master binding will not be affected by this change.

Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
2021-12-20 17:49:28 +01:00
..
acsip boards: arm: stm32: add pinctrl state name for SPI peripheral 2021-11-26 11:36:42 +01:00
atmel dts: linker region properties 2021-12-09 16:23:03 +01:00
broadcom
cypress dts: linker region properties 2021-12-09 16:23:03 +01:00
gigadevice dts: arm: gigadevice: introduce dac for gd32 series soc 2021-12-16 10:13:56 +01:00
infineon
microchip drivers: spi: Add MEC172x QMSPI-LDMA driver 2021-12-08 08:43:05 -05:00
nordic dts: nordic: Set default binding for all multi mode buses 2021-12-20 17:49:28 +01:00
nuvoton dts: arm: npcx: Fix GPIOE3 low voltage control map 2021-12-20 17:44:42 +01:00
nxp dts: bindings: can: remove #address-cells and #size-cells 2021-12-20 17:45:05 +01:00
quicklogic
renesas/gen3 dts: bindings: can: remove #address-cells and #size-cells 2021-12-20 17:45:05 +01:00
seeed dts/arm/seeed: lora-e5: Update hse clock configuration 2021-08-24 07:19:12 -04:00
silabs boards: efr32mg_sltb004a: Add minimal pwm support 2021-09-03 10:11:15 -04:00
st dts: stm32u5 has one iwdg watchdog node 2021-12-20 17:48:59 +01:00
ti dts: linker region properties 2021-12-09 16:23:03 +01:00
xilinx dts: linker region properties 2021-12-09 16:23:03 +01:00
armv6-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00
armv7-a.dtsi soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data 2021-10-28 15:26:50 +02:00
armv7-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00
armv7-r.dtsi
armv8-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00
armv8.1-m.dtsi dts: arm: Add #address-cells to nvic nodes 2021-08-02 15:02:09 -04:00