Set bus master 4 to write and read access which allows the USBFSOTG controller read/write access to the memory. Signed-off-by: Johann Fischer <j.fischer@phytec.de> |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| nios2 | ||
| posix | ||
| riscv32 | ||
| x86 | ||
| xtensa | ||
| cpu.h | ||
Set bus master 4 to write and read access which allows the USBFSOTG controller read/write access to the memory. Signed-off-by: Johann Fischer <j.fischer@phytec.de> |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| nios2 | ||
| posix | ||
| riscv32 | ||
| x86 | ||
| xtensa | ||
| cpu.h | ||