Jimmy Zheng 82c2f388ee tests: kernel: gen_isr_table.riscv_direct: exclude adp_xc7k_ae350 ... Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored mode from csr $mtvec. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>		2023-07-17 10:10:31 +00:00
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boards
src	barriers: Move __ISB() to the new API	2023-05-24 13:13:57 -04:00
CMakeLists.txt
prj.conf
testcase.yaml	tests: kernel: gen_isr_table.riscv_direct: exclude adp_xc7k_ae350	2023-07-17 10:10:31 +00:00