zephyr/soc/xtensa
Marek Matej 6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
..
espressif_esp32 soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00
intel_adsp soc: xtensa: intel_adsp: cavs: fix PM hooks guards 2023-07-20 10:33:00 +00:00
nxp_adsp soc/xtensa/nxp_adsp/CMakeLists.txt: use new WEST_SIGN_OPTS variable 2023-07-13 14:19:26 +02:00
sample_controller xtensa: linker: Use zephyr's convention for rodata 2022-11-17 15:44:48 +09:00
CMakeLists.txt