e1b95eb6df
Implement absolute minimum necessary to get Buffer DMA working. Require Data Cache to be disabled if DWC2 OTG has DMA enabled because the stack does not currently guarantee cache line alignment for allocated buffers. Set EPENA bit before disabling IN endpoints because it seems to be necessary in Buffer DMA mode (without EPENA the wait for INEPNAKEFF does time out). Setting EPENA should have no impact on Completer mode operation (where EPENA is not necessary for INEPNAKEFF to trigger). Programming Guide recommends programming SUPCnt to 3, but the only advantage would be to be able to tell how many back-to-back SETUP packets were received if there was no more than 3 back-to-back SETUPs. This information doesn't seem to be useful. The disadvantage is that the buffer needed for receiving SETUP packet must be able to hold SUPCnt multiple of 8 bytes. Use SUPCnt 1 so the 8 bytes buffer is enough. Make sure to clear StsPhseRcvd interrupt bit in Buffer DMA mode because the DMA seems to prevent the SETUP Phase Done interrupt from triggering if StsPhseRcvd is set. Clearing this bit doesn't seem to be necessary in Completer mode. This bit is set on control transfers with data stage from host to device. Both Buffer DMA and Completer mode operation on nRF54H20DK was verified using USB2CV Chapter 9 Tests and MSC Tests with Mass Storage sample. Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no> |
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| .. | ||
| bc12 | ||
| common | ||
| device | ||
| udc | ||
| uhc | ||
| uvb | ||
| CMakeLists.txt | ||
| Kconfig | ||