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TI OMAP mailbox is the inter-processor mailbox IP found in TI K3 devices (AM62X, AM64X, J721E .etc). The mailbox hardware uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The interrupt/bank associated with each processor entity is found through the usr_id property from device tree. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> |
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| .. | ||
| andestech,mbox-plic-sw.yaml | ||
| espressif,mbox-esp32.yaml | ||
| linaro,ivshmem-mbox.yaml | ||
| mailbox-controller.yaml | ||
| microchip,mpfs-mailbox.yaml | ||
| nordic,mbox-nrf-ipc.yaml | ||
| nordic,nrf-bellboard-common.yaml | ||
| nordic,nrf-bellboard-rx.yaml | ||
| nordic,nrf-bellboard-tx.yaml | ||
| nordic,nrf-vevif-event-rx.yaml | ||
| nordic,nrf-vevif-event-tx.yaml | ||
| nordic,nrf-vevif-task-rx.yaml | ||
| nordic,nrf-vevif-task-tx.yaml | ||
| nxp,mbox-imx-mu.yaml | ||
| nxp,mbox-mailbox.yaml | ||
| nxp,s32-mru.yaml | ||
| st,mbox-stm32-hsem.yaml | ||
| ti,omap-mailbox.yaml | ||