570a508633
This commit should deal with the followings: 1. Change regulator's driver priority as it should now be used by the clock control driver. 2. Check if the VDD level is permitted to change when PLL is the system clock. This is because the PLL requires that VDD be 1.2V. Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
17 lines
478 B
Plaintext
17 lines
478 B
Plaintext
# Copyright 2023 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config REGULATOR_DA1469X
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bool "DA1469X regulators driver"
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default y
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depends on DT_HAS_RENESAS_SMARTBOND_REGULATOR_ENABLED
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help
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Enable support for the Smartbond DA1469x regulators.
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config REGULATOR_DA1469X_INIT_PRIORITY
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int "Renesas DA1469x regulators driver init priority"
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default 20
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depends on REGULATOR_DA1469X
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help
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Init priority for the Renesas DA1469x regulators driver.
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