8b39d4a613
Xtensa cache line sizes aren't an obtuse area of pedantry like they are in x86. Different cores already in Zephyr are already using variant cache line sizes (64 and 128 bytes are both common). And I tripped over this by using the wrong value because the kconfig was being inherited (incorrectly) from a default somewhere. Xtensa exposes the correct value in core-isa.h (well, unless the toolchain/hal gets messed up). Add a check to make sure that our platform kconfig gets it right. Note that qemu/dc233c was already getting this wrong, leaving the value at the kconfig default of zero. That was benign (qemu doesn't provide any cache emulation for incoherent DMA), but needs to be fixed. Signed-off-by: Andy Ross <andyross@google.com>
96 lines
2.3 KiB
C
96 lines
2.3 KiB
C
/*
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* Copyright (c) 2024 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <kernel_internal.h>
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#include <zephyr/platform/hooks.h>
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#include <zephyr/arch/cache.h>
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extern FUNC_NORETURN void z_cstart(void);
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/* defined by the SoC in case of CONFIG_SOC_HAS_RUNTIME_NUM_CPUS=y */
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extern void soc_num_cpus_init(void);
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/* Make sure the platform configuration matches what the toolchain
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* thinks the hardware is doing.
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*/
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#ifdef CONFIG_DCACHE_LINE_SIZE
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BUILD_ASSERT(CONFIG_DCACHE_LINE_SIZE == XCHAL_DCACHE_LINESIZE);
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#endif
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/**
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*
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*
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*/
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void z_prep_c(void)
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{
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#if defined(CONFIG_SOC_PREP_HOOK)
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soc_prep_hook();
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#endif
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#if CONFIG_SOC_HAS_RUNTIME_NUM_CPUS
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soc_num_cpus_init();
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#endif
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_cpu_t *cpu0 = &_kernel.cpus[0];
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#ifdef CONFIG_KERNEL_COHERENCE
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/* Make sure we don't have live data for unexpected cached
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* regions due to boot firmware
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*/
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sys_cache_data_flush_and_invd_all();
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/* Our cache top stash location might have junk in it from a
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* pre-boot environment. Must be zero or valid!
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*/
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XTENSA_WSR(ZSR_FLUSH_STR, 0);
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#endif
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cpu0->nested = 0;
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/* The asm2 scheme keeps the kernel pointer in a scratch SR
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* (see zsr.h for generation specifics) for easy access. That
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* saves 4 bytes of immediate value to store the address when
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* compared to the legacy scheme. But in SMP this record is a
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* per-CPU thing and having it stored in a SR already is a big
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* win.
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*/
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XTENSA_WSR(ZSR_CPU_STR, cpu0);
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#ifdef CONFIG_INIT_STACKS
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char *stack_start = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]);
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size_t stack_sz = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]);
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char *stack_end = stack_start + stack_sz;
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uint32_t sp;
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__asm__ volatile("mov %0, sp" : "=a"(sp));
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/* Only clear the interrupt stack if the current stack pointer
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* is not within the interrupt stack. Or else we would be
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* wiping the in-use stack.
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*/
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if (((uintptr_t)sp < (uintptr_t)stack_start) ||
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((uintptr_t)sp >= (uintptr_t)stack_end)) {
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memset(stack_start, 0xAA, stack_sz);
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}
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#endif
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#if CONFIG_ARCH_CACHE
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arch_cache_init();
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#endif
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#ifdef CONFIG_XTENSA_MMU
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xtensa_mmu_init();
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#endif
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#ifdef CONFIG_XTENSA_MPU
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xtensa_mpu_init();
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#endif
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z_cstart();
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CODE_UNREACHABLE;
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}
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