William Tambe abeccfec28 xtensa: support for more than 32 interrupts ... This change add support for using more than 32 interrupts. Signed-off-by: William Tambe <williamt@cadence.com>		2025-06-27 08:59:56 -10:00
..
include	soc: intel_adsp: ace30: set MMU permissions for rom_ext sections	2025-04-04 09:35:29 +02:00
_soc_inthandlers.h	xtensa: support for more than 32 interrupts	2025-06-27 08:59:56 -10:00
ace-link.ld	SoC: Intel: ADSP: ACE30: add .imrdata to MMU definitions	2025-06-10 12:52:38 -04:00
asm_memory_management.h
boot.c
CMakeLists.txt	intel_adsp: ace: add gdb support	2025-06-23 12:32:44 -07:00
comm_widget_messages.c
comm_widget.c
comm_widget.h
gdbstub.c	intel_adsp: ace: add gdb support	2025-06-23 12:32:44 -07:00
irq.c
Kconfig	intel_adsp: ace: add gdb support	2025-06-23 12:32:44 -07:00
Kconfig.defconfig.ace15_mtpm
Kconfig.defconfig.ace20_lnl
Kconfig.defconfig.ace30	intel_adsp: ace30: Bring up ACE 3.0 (WCL)	2025-05-15 22:14:44 +02:00
Kconfig.defconfig.series	intel_adsp: ace: add gdb support	2025-06-23 12:32:44 -07:00
Kconfig.soc
linker.ld
mmu_ace30.c	SoC: Intel: ADSP: ACE30: add .imrdata to MMU definitions	2025-06-10 12:52:38 -04:00
multiprocessing.c	soc: intel_adsp: Manage power gating based on core activity	2025-06-06 08:43:15 +02:00
pmc_interface.h
power_down.S
power.c	soc: intel_adsp: Update comment style and fix typos	2025-06-06 08:43:15 +02:00
spin_relax.c	soc: intel_adsp/ace: use custom arch_spin_relax()	2025-04-21 07:45:23 +02:00
sram.c
timestamp.c