dbb8ee38f2
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
314 lines
6.8 KiB
Plaintext
314 lines
6.8 KiB
Plaintext
/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <skeleton.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/reset/mchp_mss_reset.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,e51", "riscv";
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device_type = "cpu";
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reg = < 0x0 >;
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riscv,isa = "rv64imac_zicsr_zifencei";
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hlic0: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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reg = < 0x1 >;
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riscv,isa = "rv64gc";
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hlic1: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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reg = < 0x2 >;
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riscv,isa = "rv64gc";
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hlic2: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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reg = < 0x3 >;
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riscv,isa = "rv64gc";
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hlic3: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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reg = < 0x4 >;
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riscv,isa = "rv64gc";
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hlic4: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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sram0: memory@8000000 {
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compatible = "mmio-sram";
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reg = <0x8000000 0x80000>;
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};
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sram1: memory@80000000 {
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compatible = "mmio-sram";
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reg = <0x80000000 0x800000>;
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};
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clint: clint@2000000 {
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compatible = "sifive,clint0";
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interrupts-extended = <&hlic0 3 &hlic0 7
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&hlic1 3 &hlic1 7
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&hlic2 3 &hlic2 7
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&hlic3 3 &hlic3 7
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&hlic4 3 &hlic4 7>;
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interrupt-names = "soft0", "timer0", "soft1", "timer1",
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"soft2", "timer2", "soft3", "timer3",
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"soft4", "timer4";
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reg = <0x2000000 0x10000>;
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};
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mtimer: timer@200bff8 {
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compatible = "riscv,machine-timer";
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interrupts-extended = <&hlic0 7
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&hlic1 7
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&hlic2 7
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&hlic3 7
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&hlic4 7>;
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reg = <0x200bff8 0x8 0x2004000 0x8>;
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reg-names = "mtime", "mtimecmp";
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};
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plic: interrupt-controller@c000000 {
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compatible = "sifive,plic-1.0.0";
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#interrupt-cells = <2>;
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#address-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&hlic0 11
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&hlic1 11 &hlic1 9
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&hlic2 11 &hlic2 9
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&hlic3 11 &hlic3 9
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&hlic4 11 &hlic4 9>;
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reg = <0x0c000000 0x04000000>;
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riscv,max-priority = <7>;
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riscv,ndev = <186>;
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};
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mbox: mailbox@37020000 {
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compatible = "microchip,mpfs-mailbox";
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reg = <0x37020000 0x58>, <0x2000318C 0x40>,
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<0x37020800 0x100>;
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interrupt-parent = <&plic>;
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interrupts = <96 1>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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mpfs_top_sysreg: syscon@20002000 {
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compatible = "syscon";
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reg = <0x20002000 0x1000>;
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reset: reset {
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compatible = "microchip,mpfs-reset";
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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uart0: uart@20000000 {
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compatible = "ns16550";
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reg = <0x20000000 0x1000>;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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interrupt-parent = <&plic>;
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interrupts = <90 1>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: uart@20100000 {
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compatible = "ns16550";
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reg = <0x20100000 0x1000>;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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interrupt-parent = <&plic>;
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interrupts = <91 1>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: uart@20102000 {
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compatible = "ns16550";
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reg = <0x20102000 0x1000>;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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interrupt-parent = <&plic>;
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interrupts = <92 1>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart3: uart@20104000 {
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compatible = "ns16550";
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reg = <0x20104000 0x1000>;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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interrupt-parent = <&plic>;
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interrupts = <93 1>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart4: uart@20106000 {
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compatible = "ns16550";
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reg = <0x20106000 0x1000>;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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interrupt-parent = <&plic>;
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interrupts = <94 1>;
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reg-shift = <2>;
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status = "disabled";
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};
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qspi0: spi@21000000 {
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compatible = "microchip,mpfs-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x21000000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <85 1>;
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status = "disabled";
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clock-frequency = <150000000>;
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};
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spi1: spi@20109000 {
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compatible = "microchip,mpfs-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20109000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <55 1>;
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status = "disabled";
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clock-frequency = <150000000>;
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};
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syscontroller_qspi: spi@37020100 {
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compatible = "microchip,mpfs-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x37020100 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <110 1>;
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status = "disabled";
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clock-frequency = <150000000>;
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};
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gpio0: gpio@20120000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x20120000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <51 1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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gpio1: gpio@20121000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x20121000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <52 1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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gpio2: gpio@20122000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x20122000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <53 1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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i2c0: i2c@2010a000 {
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compatible = "microchip,mpfs-i2c";
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reg = <0x2010a000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <58 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@2010b000 {
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compatible = "microchip,mpfs-i2c";
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reg = <0x2010b000 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <61 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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};
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};
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