a58e65908c
This adds a proper, concise, title property to a bunch of bindings for which the first sentence of their description (which used to be a makeshift title) was really long Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
91 lines
2.4 KiB
YAML
91 lines
2.4 KiB
YAML
# Copyright 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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title: NXP FlexRAM on-chip RAM controller
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description: |
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If the flexram,bank-spec property is specified, then the flexram will be
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dynamically reconfigured to the configuration specified at runtime. An
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example to configure the flexram dynamically using the
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flexram,bank-spec property for rt1060 is as follows:
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&itcm {
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reg = < 0x0 DT_SIZE_K(64) >;
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};
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&dtcm {
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reg = < 0x20000000 DT_SIZE_K(384) >;
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};
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&ocram {
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reg = < 0x20280000 DT_SIZE_K(64) >;
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};
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&flexram {
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flexram,bank-spec = <FLEXRAM_OCRAM>,
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<FLEXRAM_OCRAM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_ITCM>,
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<FLEXRAM_ITCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>,
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<FLEXRAM_DTCM>;
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};
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This will configure the flexram for 384K of DTCM, 64K of ITCM,
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and 64K of OCRAM.
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include: base.yaml
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compatible: "nxp,flexram"
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properties:
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reg:
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required: true
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interrupts:
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required: true
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flexram,has-magic-addr:
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type: boolean
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description: |
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Whether or not the flexram on the SOC has the
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magic address feature, which allows for an interrupt
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on arbitrary address access in any on chip RAM region.
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flexram,num-ram-banks:
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type: int
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required: true
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description: |
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Number of RAM banks in the SOC ram array
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flexram,bank-size:
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type: int
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required: true
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description: |
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Size of each RAM bank in KB
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flexram,bank-spec:
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type: array
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description: |
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Custom mapping of runtime RAM bank partitions. If this
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property is present, then it will be used. If this
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property is not present, then the fusemap configuration
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will be used.
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flexram,tcm-read-wait-mode:
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type: boolean
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description: |
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TCM RAM read will finish in 2 cycles instead of 1.
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flexram,tcm-write-wait-mode:
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type: boolean
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description: |
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TCM RAM write will finish in 2 cycles instead of 1.
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