dbb8ee38f2
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
17 lines
869 B
CMake
17 lines
869 B
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/reset.h)
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_RESET_GD32 reset_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_RPI_PICO reset_rpi_pico.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_AST10X0 reset_ast10x0.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_STM32 reset_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NUMAKER reset_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_INTEL_SOCFPGA reset_intel_socfpga.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NXP_SYSCON reset_lpc_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_MMIO reset_mmio.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_MCHP_MSS reset_mchp_mss.c)
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