b1cd947771
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate mode driver and the appropriate pinctrl bindings. Note that the CH32V003 GPIO pins have both a floating input and an analogue input mode, and the pinctrl is needed to put the pin in analogue mode. Signed-off-by: Michael Hope <michaelh@juju.nz>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (c) 2024 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT wch_afio
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>
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#include <hal_ch32fun.h>
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static GPIO_TypeDef *const wch_afio_pinctrl_regs[] = {
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(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioa)),
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(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioc)),
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(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiod)),
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};
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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int i;
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for (i = 0; i < pin_cnt; i++, pins++) {
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uint8_t port = (pins->config >> CH32V003_PINCTRL_PORT_SHIFT) & 0x03;
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uint8_t pin = (pins->config >> CH32V003_PINCTRL_PIN_SHIFT) & 0x0F;
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uint8_t bit0 = (pins->config >> CH32V003_PINCTRL_RM_BASE_SHIFT) & 0x1F;
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uint8_t remap = (pins->config >> CH32V003_PINCTRL_RM_SHIFT) & 0x3;
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GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port];
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uint8_t cfg = 0;
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bool is_adc = (bit0 == CH32V003_PINMUX_ADC1_RM);
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if (pins->output_high || pins->output_low) {
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cfg |= (pins->slew_rate + 1);
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if (pins->drive_open_drain) {
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cfg |= BIT(2);
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}
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/* Select the alternate function */
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cfg |= BIT(3);
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} else {
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if (pins->bias_pull_up || pins->bias_pull_down) {
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/* "With pull up and pull down" mode */
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cfg |= BIT(3);
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} else if (is_adc) {
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/* Analog input mode */
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cfg = 0;
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} else {
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/* Floating input mode */
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cfg |= BIT(2);
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}
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}
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regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4));
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if (pins->output_high) {
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regs->BSHR = BIT(pin);
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} else if (pins->output_low) {
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/* Reset the pin. */
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regs->BCR = BIT(pin);
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} else {
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if (pins->bias_pull_up) {
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regs->BSHR = BIT(pin);
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}
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if (pins->bias_pull_down) {
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regs->BCR = BIT(pin);
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}
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}
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if (remap != 0) {
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RCC->APB2PCENR |= RCC_AFIOEN;
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if (bit0 == CH32V003_PINMUX_I2C1_RM) {
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AFIO->PCFR1 |= ((uint32_t)((remap >> 0) & 1)
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<< CH32V003_PINMUX_I2C1_RM) |
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((uint32_t)((remap >> 1) & 1)
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<< CH32V003_PINMUX_I2C1_RM1);
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} else if (bit0 == CH32V003_PINMUX_USART1_RM) {
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AFIO->PCFR1 |= ((uint32_t)((remap >> 0) & 1)
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<< CH32V003_PINMUX_USART1_RM) |
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((uint32_t)((remap >> 1) & 1)
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<< CH32V003_PINMUX_USART1_RM1);
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} else {
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AFIO->PCFR1 |= (uint32_t)remap << bit0;
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}
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}
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}
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return 0;
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}
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static int pinctrl_clock_init(void)
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{
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const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
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uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id);
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return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id);
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}
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SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
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