99957e1fb3
Fix ABUS allocation if both EVEN and ODD busses are used for the same port. The initialisation loop would incorrectly overwrite entire GPIO_nBUSALLOC when iterating the pinctrl array, must do a read/mask/update/write sequence. Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/arch/cpu.h>
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#include <em_gpio.h>
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#define DT_DRV_COMPAT silabs_dbus_pinctrl
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#define PIN_MASK 0xF0000UL
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#define ABUS_MASK(i) GENMASK(((i) * 8) + 3, (i) * 8)
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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mem_addr_t enable_reg, route_reg;
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/* Configure ABUS */
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if (pins[i].en_bit == SILABS_PINCTRL_ANALOG) {
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enable_reg = DT_INST_REG_ADDR_BY_NAME(0, abus) +
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(pins[i].base_offset * sizeof(mem_addr_t));
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/* Read-modify-write. */
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uint32_t reg_val = sys_read32(enable_reg);
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reg_val &= ~ABUS_MASK(pins[i].mode);
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reg_val |= FIELD_PREP(ABUS_MASK(pins[i].mode), pins[i].route_offset);
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sys_write32(reg_val, enable_reg);
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continue;
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}
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/* Configure GPIO */
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GPIO_PinModeSet(pins[i].port, pins[i].pin, pins[i].mode, pins[i].dout);
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/* Configure DBUS */
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enable_reg = DT_INST_REG_ADDR_BY_NAME(0, dbus) +
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(pins[i].base_offset * sizeof(mem_addr_t));
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route_reg = enable_reg + (pins[i].route_offset * sizeof(mem_addr_t));
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if (pins[i].route_offset != SILABS_PINCTRL_UNUSED) {
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sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg);
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}
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if (pins[i].en_bit != SILABS_PINCTRL_UNUSED) {
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if (pins[i].mode == gpioModeDisabled) {
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sys_clear_bit(enable_reg, pins[i].en_bit);
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} else {
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sys_set_bit(enable_reg, pins[i].en_bit);
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}
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}
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}
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return 0;
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}
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