e0f02d93a6
Two DMA channels are assigned to AES channels A and B respectively. Each channel A/B has an interface to control the conditions that will generate requests on the related DMA channel: trigger condition, R/W address, and DMA done action. Signed-off-by: Julien Panis <jpanis@baylibre.com>
1045 lines
27 KiB
C
1045 lines
27 KiB
C
/*
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_aes
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(crypto_cc23x0, CONFIG_CRYPTO_LOG_LEVEL);
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#include <zephyr/crypto/crypto.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/irq.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#include <string.h>
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#include <driverlib/aes.h>
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#include <driverlib/clkctl.h>
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#include <inc/hw_memmap.h>
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#define CRYPTO_CC23_CAP (CAP_RAW_KEY | CAP_SEPARATE_IO_BUFS | \
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CAP_SYNC_OPS | CAP_NO_IV_PREFIX)
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/* CCM mode: see https://datatracker.ietf.org/doc/html/rfc3610 for reference */
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#define CCM_CC23_MSG_LEN_SIZE_MIN 2
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#define CCM_CC23_MSG_LEN_SIZE_MAX 8
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#define CCM_CC23_NONCE_LEN_SIZE_MIN (AES_BLOCK_SIZE - CCM_CC23_MSG_LEN_SIZE_MAX - 1)
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#define CCM_CC23_NONCE_LEN_SIZE_MAX (AES_BLOCK_SIZE - CCM_CC23_MSG_LEN_SIZE_MIN - 1)
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#define CCM_CC23_AD_LEN_SIZE 2
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#define CCM_CC23_AD_DATA_SIZE_MAX (AES_BLOCK_SIZE - CCM_CC23_AD_LEN_SIZE)
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#define CCM_CC23_TAG_SIZE_MIN 4
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#define CCM_CC23_TAG_SIZE_MAX 16
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#define CCM_CC23_BYTE_GET(idx, val) FIELD_GET(0xff << ((idx) << 3), (val))
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#define CCM_CC23_B0_GET(ad_len, tag_len, len_size) \
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(((ad_len) ? 1 << 6 : 0) + (((tag_len) - 2) << 2) + ((len_size) - 1))
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/*
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* The Finite State Machine (FSM) processes the data in a column-fashioned way,
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* processing 2 columns/cycle, completing 10 rounds in 20 cycles. With three cycles
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* of pre-processing, the execution/encryption time is 23 cycles.
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*/
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#define CRYPTO_CC23_BLK_PROC_CYC 23
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#define CRYPTO_CC23_BLK_PROC_TIMEOUT (CRYPTO_CC23_BLK_PROC_CYC << 1)
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#define CRYPTO_CC23_OP_TIMEOUT K_CYC(CRYPTO_CC23_BLK_PROC_TIMEOUT)
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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#define CRYPTO_CC23_OP_TIMEOUT_DMA(len) \
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K_CYC(CRYPTO_CC23_BLK_PROC_TIMEOUT * ((len) / AES_BLOCK_SIZE))
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#define CRYPTO_CC23_IS_INVALID_DATA_LEN_DMA(len) ((len) % AES_BLOCK_SIZE)
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#define CRYPTO_CC23_REG_GET(offset) (AES_BASE + (offset))
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struct crypto_cc23x0_config {
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const struct device *dma_dev;
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uint8_t dma_channel_a;
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uint8_t dma_trigsrc_a;
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uint8_t dma_channel_b;
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uint8_t dma_trigsrc_b;
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};
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#endif
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struct crypto_cc23x0_data {
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struct k_mutex device_mutex;
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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struct k_sem cha_done;
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struct k_sem chb_done;
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#else
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struct k_sem aes_done;
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#endif
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};
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static void crypto_cc23x0_isr(const struct device *dev)
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{
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struct crypto_cc23x0_data *data = dev->data;
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uint32_t status;
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status = AESGetMaskedInterruptStatus();
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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if (status & AES_IMASK_CHADONE) {
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k_sem_give(&data->cha_done);
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} else if (status & AES_IMASK_CHBDONE) {
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k_sem_give(&data->chb_done);
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}
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#else
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if (status & AES_IMASK_AESDONE) {
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k_sem_give(&data->aes_done);
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}
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#endif
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AESClearInterrupt(status);
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}
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static void crypto_cc23x0_cleanup(const struct device *dev)
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{
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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const struct crypto_cc23x0_config *cfg = dev->config;
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dma_stop(cfg->dma_dev, cfg->dma_channel_b);
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dma_stop(cfg->dma_dev, cfg->dma_channel_a);
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AESDisableDMA();
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#else
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ARG_UNUSED(dev);
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#endif
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AESClearAUTOCFGTrigger();
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AESClearAUTOCFGBusHalt();
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AESClearTXTAndBUF();
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}
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static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt *pkt)
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{
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const struct device *dev = ctx->device;
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struct crypto_cc23x0_data *data = dev->data;
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int out_bytes_processed = 0;
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int ret;
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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uint32_t int_flags = AES_IMASK_CHBDONE;
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const struct crypto_cc23x0_config *cfg = dev->config;
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struct dma_block_config block_cfg_cha = {
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.source_address = (uint32_t)(pkt->in_buf),
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.dest_address = CRYPTO_CC23_REG_GET(AES_O_DMACHA),
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.source_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.block_size = pkt->in_len,
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};
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struct dma_config dma_cfg_cha = {
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.dma_slot = cfg->dma_trigsrc_a,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.block_count = 1,
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.head_block = &block_cfg_cha,
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.source_data_size = sizeof(uint32_t),
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.dest_data_size = sizeof(uint32_t),
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.source_burst_length = AES_BLOCK_SIZE,
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.dma_callback = NULL,
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.user_data = NULL,
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};
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struct dma_block_config block_cfg_chb = {
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.source_address = CRYPTO_CC23_REG_GET(AES_O_DMACHB),
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.dest_address = (uint32_t)(pkt->out_buf),
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.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.block_size = pkt->in_len,
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};
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struct dma_config dma_cfg_chb = {
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.dma_slot = cfg->dma_trigsrc_b,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.block_count = 1,
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.head_block = &block_cfg_chb,
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.source_data_size = sizeof(uint32_t),
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.dest_data_size = sizeof(uint32_t),
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.source_burst_length = AES_BLOCK_SIZE,
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.dma_callback = NULL,
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.user_data = NULL,
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};
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#else
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uint32_t int_flags = AES_IMASK_AESDONE;
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int in_bytes_processed = 0;
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#endif
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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if (CRYPTO_CC23_IS_INVALID_DATA_LEN_DMA(pkt->in_len)) {
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LOG_ERR("In DMA mode, data length must be a multiple of %d", AES_BLOCK_SIZE);
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return -EINVAL;
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}
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#endif
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if (pkt->out_buf_max < ROUND_UP(pkt->in_len, AES_BLOCK_SIZE)) {
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LOG_ERR("Output buffer too small");
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return -EINVAL;
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}
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k_mutex_lock(&data->device_mutex, K_FOREVER);
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/* Enable interrupts */
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AESSetIMASK(int_flags);
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/* Load key */
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AESWriteKEY(ctx->key.bit_stream);
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/* Configure source buffer and encryption triggers */
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AESSetAUTOCFG(AES_AUTOCFG_AESSRC_BUF |
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AES_AUTOCFG_TRGAES_RDTXT3 |
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AES_AUTOCFG_TRGAES_WRBUF3S);
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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/* Setup the DMA for the AES engine */
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AESSetupDMA(AES_DMA_ADRCHA_BUF0 |
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AES_DMA_TRGCHA_AESSTART |
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AES_DMA_ADRCHB_TXT0 |
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AES_DMA_TRGCHB_AESDONE |
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(pkt->in_len == AES_BLOCK_SIZE ?
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AES_DMA_DONEACT_GATE_TRGAES_ON_CHA :
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AES_DMA_DONEACT_GATE_TRGAES_ON_CHA_DEL));
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ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha);
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if (ret) {
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goto cleanup;
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}
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ret = dma_config(cfg->dma_dev, cfg->dma_channel_b, &dma_cfg_chb);
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if (ret) {
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goto cleanup;
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}
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dma_start(cfg->dma_dev, cfg->dma_channel_a);
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dma_start(cfg->dma_dev, cfg->dma_channel_b);
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/* Trigger AES operation */
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AESSetTrigger(AES_TRG_DMACHA);
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/* Wait for AES operation completion */
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ret = k_sem_take(&data->chb_done, CRYPTO_CC23_OP_TIMEOUT_DMA(pkt->in_len));
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if (ret) {
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goto cleanup;
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}
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LOG_DBG("AES operation completed");
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out_bytes_processed = pkt->in_len;
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#else
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/* Write first block of input to trigger encryption */
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AESWriteBUF(pkt->in_buf);
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in_bytes_processed += AES_BLOCK_SIZE;
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do {
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if (in_bytes_processed < pkt->in_len) {
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/* Preload next input block */
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AESWriteBUF(&pkt->in_buf[in_bytes_processed]);
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in_bytes_processed += AES_BLOCK_SIZE;
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} else {
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/* Avoid triggering a spurious encryption upon reading the final output */
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AESClearAUTOCFGTrigger();
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}
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/* Wait for AES operation completion */
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ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
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if (ret) {
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goto cleanup;
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}
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LOG_DBG("AES operation completed");
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/*
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* Read output and trigger encryption of next input that was
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* preloaded at the start of this loop.
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*/
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AESReadTXT(&pkt->out_buf[out_bytes_processed]);
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out_bytes_processed += AES_BLOCK_SIZE;
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} while (out_bytes_processed < pkt->in_len);
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#endif
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cleanup:
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crypto_cc23x0_cleanup(dev);
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k_mutex_unlock(&data->device_mutex);
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pkt->out_len = out_bytes_processed;
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return ret;
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}
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static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv)
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{
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const struct device *dev = ctx->device;
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struct crypto_cc23x0_data *data = dev->data;
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uint32_t ctr_len = ctx->mode_params.ctr_info.ctr_len >> 3;
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uint8_t ctr[AES_BLOCK_SIZE] = { 0 };
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int bytes_processed = 0;
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int iv_len;
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int ret;
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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uint32_t int_flags = AES_IMASK_CHBDONE;
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const struct crypto_cc23x0_config *cfg = dev->config;
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struct dma_block_config block_cfg_cha = {
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.source_address = (uint32_t)(pkt->in_buf),
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.dest_address = CRYPTO_CC23_REG_GET(AES_O_DMACHA),
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.source_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.block_size = pkt->in_len,
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};
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struct dma_config dma_cfg_cha = {
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.dma_slot = cfg->dma_trigsrc_a,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.block_count = 1,
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.head_block = &block_cfg_cha,
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.source_data_size = sizeof(uint32_t),
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.dest_data_size = sizeof(uint32_t),
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.source_burst_length = AES_BLOCK_SIZE,
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.dma_callback = NULL,
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.user_data = NULL,
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};
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struct dma_block_config block_cfg_chb = {
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.source_address = CRYPTO_CC23_REG_GET(AES_O_DMACHB),
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.dest_address = (uint32_t)(pkt->out_buf),
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.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.block_size = pkt->in_len,
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};
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struct dma_config dma_cfg_chb = {
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.dma_slot = cfg->dma_trigsrc_b,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.block_count = 1,
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.head_block = &block_cfg_chb,
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.source_data_size = sizeof(uint32_t),
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.dest_data_size = sizeof(uint32_t),
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.source_burst_length = AES_BLOCK_SIZE,
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.dma_callback = NULL,
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.user_data = NULL,
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};
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#else
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uint32_t int_flags = AES_IMASK_AESDONE;
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uint8_t last_buf[AES_BLOCK_SIZE] = { 0 };
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int bytes_remaining = pkt->in_len;
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int block_size;
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#endif
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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if (CRYPTO_CC23_IS_INVALID_DATA_LEN_DMA(pkt->in_len)) {
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LOG_ERR("In DMA mode, data length must be a multiple of %d", AES_BLOCK_SIZE);
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return -EINVAL;
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}
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#endif
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if (pkt->out_buf_max < ROUND_UP(pkt->in_len, AES_BLOCK_SIZE)) {
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LOG_ERR("Output buffer too small");
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return -EINVAL;
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}
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k_mutex_lock(&data->device_mutex, K_FOREVER);
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/* Enable interrupts */
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AESSetIMASK(int_flags);
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/* Load key */
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AESWriteKEY(ctx->key.bit_stream);
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/* Configure source buffer and encryption triggers */
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AESSetAUTOCFG(AES_AUTOCFG_AESSRC_BUF |
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AES_AUTOCFG_TRGAES_RDTXT3 |
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AES_AUTOCFG_TRGAES_WRBUF3S |
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AES_AUTOCFG_CTRENDN_BIGENDIAN |
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AES_AUTOCFG_CTRSIZE_CTR128);
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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/* Setup the DMA for the AES engine */
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AESSetupDMA(AES_DMA_ADRCHA_TXTX0 |
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AES_DMA_TRGCHA_AESDONE |
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AES_DMA_ADRCHB_TXT0 |
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AES_DMA_TRGCHB_WRTXT3);
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ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha);
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if (ret) {
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goto cleanup;
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}
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ret = dma_config(cfg->dma_dev, cfg->dma_channel_b, &dma_cfg_chb);
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if (ret) {
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goto cleanup;
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}
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dma_start(cfg->dma_dev, cfg->dma_channel_a);
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dma_start(cfg->dma_dev, cfg->dma_channel_b);
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#endif
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/* Write the counter value to the AES engine to trigger first encryption */
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iv_len = (ctx->ops.cipher_mode == CRYPTO_CIPHER_MODE_CCM) ?
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AES_BLOCK_SIZE : (ctx->keylen - ctr_len);
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memcpy(ctr, iv, iv_len);
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AESWriteBUF(ctr);
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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/* Wait for AES operation completion */
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ret = k_sem_take(&data->chb_done, CRYPTO_CC23_OP_TIMEOUT_DMA(pkt->in_len));
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if (ret) {
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goto cleanup;
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}
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LOG_DBG("AES operation completed");
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bytes_processed = pkt->in_len;
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#else
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do {
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/* Wait for AES operation completion */
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ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
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if (ret) {
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goto cleanup;
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}
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LOG_DBG("AES operation completed");
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/* XOR input data with encrypted counter block to form ciphertext */
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if (bytes_remaining > AES_BLOCK_SIZE) {
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block_size = AES_BLOCK_SIZE;
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AESWriteTXTXOR(&pkt->in_buf[bytes_processed]);
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} else {
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block_size = bytes_remaining;
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memcpy(last_buf, &pkt->in_buf[bytes_processed], block_size);
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AESWriteTXTXOR(last_buf);
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/*
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* Do not auto-trigger encrypt and increment of counter
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* value for last block of data.
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*/
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AESClearAUTOCFGTrigger();
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}
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/*
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* Read the output ciphertext and trigger the encryption
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* of the next counter block
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*/
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AESReadTXT(&pkt->out_buf[bytes_processed]);
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bytes_processed += block_size;
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bytes_remaining -= block_size;
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} while (bytes_remaining > 0);
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#endif
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cleanup:
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crypto_cc23x0_cleanup(dev);
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k_mutex_unlock(&data->device_mutex);
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pkt->out_len = bytes_processed;
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return ret;
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}
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|
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static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt,
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uint8_t *b0, uint8_t *b1)
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{
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const struct device *dev = ctx->device;
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struct crypto_cc23x0_data *data = dev->data;
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uint32_t iv[AES_BLOCK_SIZE_WORDS] = { 0 };
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int bytes_processed = 0;
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int ret;
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#ifdef CONFIG_CRYPTO_CC23X0_DMA
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uint32_t int_flags = AES_IMASK_CHADONE;
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const struct crypto_cc23x0_config *cfg = dev->config;
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|
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struct dma_block_config block_cfg_cha = {
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.source_address = (uint32_t)b0,
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.dest_address = CRYPTO_CC23_REG_GET(AES_O_DMACHA),
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.source_addr_adj = DMA_ADDR_ADJ_INCREMENT,
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.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE,
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.block_size = AES_BLOCK_SIZE,
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};
|
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|
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struct dma_config dma_cfg_cha = {
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.dma_slot = cfg->dma_trigsrc_a,
|
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.channel_direction = MEMORY_TO_PERIPHERAL,
|
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.block_count = 1,
|
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.head_block = &block_cfg_cha,
|
|
.source_data_size = sizeof(uint32_t),
|
|
.dest_data_size = sizeof(uint32_t),
|
|
.source_burst_length = AES_BLOCK_SIZE,
|
|
.dma_callback = NULL,
|
|
.user_data = NULL,
|
|
};
|
|
#else
|
|
uint32_t int_flags = AES_IMASK_AESDONE;
|
|
uint8_t last_buf[AES_BLOCK_SIZE] = { 0 };
|
|
int bytes_remaining = pkt->in_len;
|
|
int block_size;
|
|
#endif
|
|
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
if (CRYPTO_CC23_IS_INVALID_DATA_LEN_DMA(pkt->in_len)) {
|
|
LOG_ERR("In DMA mode, data length must be a multiple of %d", AES_BLOCK_SIZE);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
if (pkt->out_buf_max < AES_BLOCK_SIZE) {
|
|
LOG_ERR("Output buffer too small");
|
|
return -EINVAL;
|
|
}
|
|
|
|
k_mutex_lock(&data->device_mutex, K_FOREVER);
|
|
|
|
/* Enable interrupts */
|
|
AESSetIMASK(int_flags);
|
|
|
|
/* Load key */
|
|
AESWriteKEY(ctx->key.bit_stream);
|
|
|
|
/* Configure source buffer and encryption triggers */
|
|
AESSetAUTOCFG(AES_AUTOCFG_AESSRC_TXTXBUF |
|
|
AES_AUTOCFG_TRGAES_WRBUF3 |
|
|
AES_AUTOCFG_BUSHALT_EN);
|
|
|
|
/* Write zero'd IV */
|
|
AESWriteIV32(iv);
|
|
|
|
if (b0) {
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
/* Setup the DMA for the AES engine */
|
|
AESSetupDMA(AES_DMA_ADRCHA_BUF0 |
|
|
AES_DMA_TRGCHA_AESSTART);
|
|
|
|
ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
|
|
dma_start(cfg->dma_dev, cfg->dma_channel_a);
|
|
|
|
/* Trigger AES operation */
|
|
AESSetTrigger(AES_TRG_DMACHA);
|
|
|
|
/* Wait for AES operation completion */
|
|
ret = k_sem_take(&data->cha_done, CRYPTO_CC23_OP_TIMEOUT_DMA(AES_BLOCK_SIZE));
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
#else
|
|
/* Load input block */
|
|
AESWriteBUF(b0);
|
|
|
|
/* Wait for AES operation completion */
|
|
ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
#endif
|
|
LOG_DBG("AES operation completed (block 0)");
|
|
}
|
|
|
|
if (b1) {
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
block_cfg_cha.source_address = (uint32_t)b1;
|
|
|
|
ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
|
|
dma_start(cfg->dma_dev, cfg->dma_channel_a);
|
|
|
|
/* Trigger AES operation */
|
|
AESSetTrigger(AES_TRG_DMACHA);
|
|
|
|
/* Wait for AES operation completion */
|
|
ret = k_sem_take(&data->cha_done, CRYPTO_CC23_OP_TIMEOUT_DMA(AES_BLOCK_SIZE));
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
#else
|
|
/* Load input block */
|
|
AESWriteBUF(b1);
|
|
|
|
/* Wait for AES operation completion */
|
|
ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
#endif
|
|
LOG_DBG("AES operation completed (block 1)");
|
|
}
|
|
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
block_cfg_cha.source_address = (uint32_t)(pkt->in_buf);
|
|
block_cfg_cha.block_size = pkt->in_len;
|
|
|
|
ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
|
|
dma_start(cfg->dma_dev, cfg->dma_channel_a);
|
|
|
|
/* Trigger AES operation */
|
|
AESSetTrigger(AES_TRG_DMACHA);
|
|
|
|
/* Wait for AES operation completion */
|
|
ret = k_sem_take(&data->cha_done, CRYPTO_CC23_OP_TIMEOUT_DMA(pkt->in_len));
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
|
|
LOG_DBG("AES operation completed (data)");
|
|
|
|
bytes_processed = pkt->in_len;
|
|
#else
|
|
do {
|
|
/* Load input block */
|
|
if (bytes_remaining >= AES_BLOCK_SIZE) {
|
|
block_size = AES_BLOCK_SIZE;
|
|
AESWriteBUF(&pkt->in_buf[bytes_processed]);
|
|
} else {
|
|
block_size = bytes_remaining;
|
|
memcpy(last_buf, &pkt->in_buf[bytes_processed], block_size);
|
|
AESWriteBUF(last_buf);
|
|
}
|
|
|
|
/* Wait for AES operation completion */
|
|
ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
|
|
LOG_DBG("AES operation completed (data)");
|
|
|
|
bytes_processed += block_size;
|
|
bytes_remaining -= block_size;
|
|
} while (bytes_remaining > 0);
|
|
#endif
|
|
|
|
/* Read tag */
|
|
AESReadTag(pkt->out_buf);
|
|
|
|
out:
|
|
crypto_cc23x0_cleanup(dev);
|
|
k_mutex_unlock(&data->device_mutex);
|
|
pkt->out_len = bytes_processed;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int crypto_cc23x0_ccm_check_param(struct cipher_ctx *ctx, struct cipher_aead_pkt *aead_op)
|
|
{
|
|
uint16_t ad_len = aead_op->ad_len;
|
|
uint16_t tag_len = ctx->mode_params.ccm_info.tag_len;
|
|
uint16_t nonce_len = ctx->mode_params.ccm_info.nonce_len;
|
|
|
|
if (aead_op->pkt->out_buf_max < ROUND_UP(aead_op->pkt->in_len, AES_BLOCK_SIZE)) {
|
|
LOG_ERR("Output buffer too small");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (tag_len < CCM_CC23_TAG_SIZE_MIN || tag_len > CCM_CC23_TAG_SIZE_MAX || tag_len & 1) {
|
|
LOG_ERR("CCM parameter invalid (tag_len must be an even value from %d to %d)",
|
|
CCM_CC23_TAG_SIZE_MIN, CCM_CC23_TAG_SIZE_MAX);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (nonce_len < CCM_CC23_NONCE_LEN_SIZE_MIN || nonce_len > CCM_CC23_NONCE_LEN_SIZE_MAX) {
|
|
LOG_ERR("CCM parameter invalid (nonce_len must be a value from %d to %d)",
|
|
CCM_CC23_NONCE_LEN_SIZE_MIN, CCM_CC23_NONCE_LEN_SIZE_MAX);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ad_len > CCM_CC23_AD_DATA_SIZE_MAX) {
|
|
LOG_ERR("CCM parameter invalid (ad_len max = %d)", CCM_CC23_AD_DATA_SIZE_MAX);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int crypto_cc23x0_ccm_encrypt(struct cipher_ctx *ctx,
|
|
struct cipher_aead_pkt *aead_op, uint8_t *nonce)
|
|
{
|
|
struct cipher_pkt tag_pkt = { 0 };
|
|
struct cipher_pkt data_pkt = { 0 };
|
|
uint8_t tag[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t b0[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t b1[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t ctri[AES_BLOCK_SIZE] = { 0 };
|
|
uint32_t msg_len = aead_op->pkt->in_len;
|
|
uint16_t ad_len = aead_op->ad_len;
|
|
uint16_t tag_len = ctx->mode_params.ccm_info.tag_len;
|
|
uint16_t nonce_len = ctx->mode_params.ccm_info.nonce_len;
|
|
uint8_t len_size = AES_BLOCK_SIZE - nonce_len - 1;
|
|
int ret;
|
|
int i;
|
|
|
|
ret = crypto_cc23x0_ccm_check_param(ctx, aead_op);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Build the first block B0 required for CMAC computation.
|
|
* ============================================
|
|
* Block B0 formatting per RFC3610:
|
|
* Octet Number Contents
|
|
* ------------ ---------
|
|
* 0 Flags
|
|
* 1 ... 15-L Nonce N
|
|
* 16-L ... 15 l(m), MSB first
|
|
*
|
|
* Flags in octet 0 of B0:
|
|
* Bit Number Contents
|
|
* ---------- ----------------------
|
|
* 7 Reserved (always zero)
|
|
* 6 Adata = 1 if l(a) > 0, 0 otherwise
|
|
* 5 ... 3 M' = (M - 2) / 2 where M = Number of octets in authentication field
|
|
* 2 ... 0 L' = L - 1 where L = Number of octets in length field
|
|
* ============================================
|
|
*/
|
|
b0[0] = CCM_CC23_B0_GET(aead_op->ad_len, tag_len, len_size);
|
|
|
|
for (i = 0 ; i < sizeof(msg_len) ; i++) {
|
|
b0[AES_BLOCK_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, msg_len);
|
|
}
|
|
|
|
memcpy(&b0[1], nonce, nonce_len);
|
|
|
|
/*
|
|
* Build the second block B1 for additional data (header).
|
|
* ============================================
|
|
* Block B1 formatting per RFC3610, for 0 < l(a) < (2^16 - 2^8):
|
|
* Octet Number Contents
|
|
* ------------ ---------
|
|
* 0 ... 1 l(a), MSB first
|
|
* 2 ... N Header data
|
|
* N+1 ... 15 Zero padding
|
|
* ============================================
|
|
*/
|
|
for (i = 0 ; i < sizeof(ad_len) ; i++) {
|
|
b1[CCM_CC23_AD_LEN_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, ad_len);
|
|
}
|
|
|
|
memcpy(&b1[CCM_CC23_AD_LEN_SIZE], aead_op->ad, ad_len);
|
|
|
|
/* Calculate the authentication tag by passing B0, B1, and data to CMAC function. */
|
|
LOG_DBG("Compute CMAC");
|
|
|
|
data_pkt.in_buf = aead_op->pkt->in_buf;
|
|
data_pkt.in_len = aead_op->pkt->in_len;
|
|
data_pkt.out_buf = tag;
|
|
data_pkt.out_buf_max = AES_BLOCK_SIZE;
|
|
|
|
ret = crypto_cc23x0_cmac(ctx, &data_pkt, b0, b1);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Prepare the initial counter block CTR1 for the CTR mode.
|
|
* ============================================
|
|
* Block CTRi formatting per RFC3610:
|
|
* Octet Number Contents
|
|
* ------------ ---------
|
|
* 0 Flags
|
|
* 1 ... 15-L Nonce N
|
|
* 16-L ... 15 Counter i, MSB first
|
|
*
|
|
* Flags in octet 0 of CTR0:
|
|
* Bit Number Contents
|
|
* ---------- ----------------------
|
|
* 7 Reserved (always zero)
|
|
* 6 Reserved (always zero)
|
|
* 5 ... 3 Zero
|
|
* 2 ... 0 L' = L - 1 where L = Number of octets in length field
|
|
* ============================================
|
|
*/
|
|
ctri[0] = len_size - 1;
|
|
memcpy(&ctri[1], nonce, nonce_len);
|
|
ctri[AES_BLOCK_SIZE - 1] = 1;
|
|
|
|
/* Encrypt the data using the counter block CTR1. */
|
|
LOG_DBG("Encrypt data");
|
|
|
|
ret = crypto_cc23x0_ctr(ctx, aead_op->pkt, ctri);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* Encrypt the authentication tag using the counter block CTR0. */
|
|
LOG_DBG("Encrypt tag");
|
|
|
|
ctri[AES_BLOCK_SIZE - 1] = 0;
|
|
|
|
tag_pkt.in_buf = tag;
|
|
tag_pkt.in_len = tag_len;
|
|
tag_pkt.out_buf = aead_op->tag;
|
|
tag_pkt.out_buf_max = AES_BLOCK_SIZE;
|
|
|
|
return crypto_cc23x0_ctr(ctx, &tag_pkt, ctri);
|
|
}
|
|
|
|
static int crypto_cc23x0_ccm_decrypt(struct cipher_ctx *ctx,
|
|
struct cipher_aead_pkt *aead_op, uint8_t *nonce)
|
|
{
|
|
struct cipher_pkt tag_pkt = { 0 };
|
|
struct cipher_pkt data_pkt = { 0 };
|
|
uint8_t enc_tag[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t calc_tag[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t b0[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t b1[AES_BLOCK_SIZE] = { 0 };
|
|
uint8_t ctri[AES_BLOCK_SIZE] = { 0 };
|
|
uint32_t msg_len = aead_op->pkt->in_len;
|
|
uint16_t ad_len = aead_op->ad_len;
|
|
uint16_t tag_len = ctx->mode_params.ccm_info.tag_len;
|
|
uint16_t nonce_len = ctx->mode_params.ccm_info.nonce_len;
|
|
uint8_t len_size = AES_BLOCK_SIZE - nonce_len - 1;
|
|
int ret;
|
|
int i;
|
|
|
|
ret = crypto_cc23x0_ccm_check_param(ctx, aead_op);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* Prepare the initial counter block CTR1 for the CTR mode. */
|
|
ctri[0] = len_size - 1;
|
|
memcpy(&ctri[1], nonce, nonce_len);
|
|
ctri[AES_BLOCK_SIZE - 1] = 1;
|
|
|
|
/* Decrypt the data using the counter block CTR1. */
|
|
LOG_DBG("Decrypt data");
|
|
|
|
ret = crypto_cc23x0_ctr(ctx, aead_op->pkt, ctri);
|
|
if (ret) {
|
|
goto clear_out_buf;
|
|
}
|
|
|
|
/* Build the first block B0 required for CMAC computation. */
|
|
b0[0] = CCM_CC23_B0_GET(aead_op->ad_len, tag_len, len_size);
|
|
|
|
for (i = 0 ; i < sizeof(msg_len) ; i++) {
|
|
b0[AES_BLOCK_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, msg_len);
|
|
}
|
|
|
|
memcpy(&b0[1], nonce, nonce_len);
|
|
|
|
/* Build the second block B1 for additional data (header). */
|
|
for (i = 0 ; i < sizeof(ad_len) ; i++) {
|
|
b1[CCM_CC23_AD_LEN_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, ad_len);
|
|
}
|
|
|
|
memcpy(&b1[CCM_CC23_AD_LEN_SIZE], aead_op->ad, ad_len);
|
|
|
|
/*
|
|
* Calculate the authentication tag by passing B0, B1, and decrypted data
|
|
* to CMAC function.
|
|
*/
|
|
LOG_DBG("Compute CMAC");
|
|
|
|
data_pkt.in_buf = aead_op->pkt->out_buf;
|
|
data_pkt.in_len = aead_op->pkt->out_len;
|
|
data_pkt.out_buf = calc_tag;
|
|
data_pkt.out_buf_max = AES_BLOCK_SIZE;
|
|
|
|
ret = crypto_cc23x0_cmac(ctx, &data_pkt, b0, b1);
|
|
if (ret) {
|
|
goto clear_out_buf;
|
|
}
|
|
|
|
/* Encrypt the recalculated authentication tag using the counter block CTR0. */
|
|
LOG_DBG("Encrypt tag");
|
|
|
|
ctri[AES_BLOCK_SIZE - 1] = 0;
|
|
|
|
tag_pkt.in_buf = calc_tag;
|
|
tag_pkt.in_len = tag_len;
|
|
tag_pkt.out_buf = enc_tag;
|
|
tag_pkt.out_buf_max = AES_BLOCK_SIZE;
|
|
|
|
ret = crypto_cc23x0_ctr(ctx, &tag_pkt, ctri);
|
|
if (ret) {
|
|
goto clear_out_buf;
|
|
}
|
|
|
|
/*
|
|
* Compare the recalculated encrypted authentication tag with the one supplied by the app.
|
|
* If they match, the decrypted data is returned. Otherwise, the authentication has failed
|
|
* and the output buffer is zero'd.
|
|
*/
|
|
LOG_DBG("Check tag");
|
|
|
|
if (!memcmp(enc_tag, aead_op->tag, tag_len)) {
|
|
return 0;
|
|
}
|
|
|
|
LOG_ERR("Invalid tag");
|
|
ret = -EINVAL;
|
|
|
|
clear_out_buf:
|
|
memset(aead_op->pkt->out_buf, 0, msg_len);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int crypto_cc23x0_session_setup(const struct device *dev,
|
|
struct cipher_ctx *ctx,
|
|
enum cipher_algo algo,
|
|
enum cipher_mode mode,
|
|
enum cipher_op op_type)
|
|
{
|
|
if (ctx->flags & ~(CRYPTO_CC23_CAP)) {
|
|
LOG_ERR("Unsupported feature");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (algo != CRYPTO_CIPHER_ALGO_AES) {
|
|
LOG_ERR("Unsupported algo");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (mode != CRYPTO_CIPHER_MODE_ECB &&
|
|
mode != CRYPTO_CIPHER_MODE_CTR &&
|
|
mode != CRYPTO_CIPHER_MODE_CCM) {
|
|
LOG_ERR("Unsupported mode");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ctx->keylen != 16U) {
|
|
LOG_ERR("%u key size is not supported", ctx->keylen);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!ctx->key.bit_stream) {
|
|
LOG_ERR("No key provided");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) {
|
|
switch (mode) {
|
|
case CRYPTO_CIPHER_MODE_ECB:
|
|
ctx->ops.block_crypt_hndlr = crypto_cc23x0_ecb_encrypt;
|
|
break;
|
|
case CRYPTO_CIPHER_MODE_CTR:
|
|
ctx->ops.ctr_crypt_hndlr = crypto_cc23x0_ctr;
|
|
break;
|
|
case CRYPTO_CIPHER_MODE_CCM:
|
|
ctx->ops.ccm_crypt_hndlr = crypto_cc23x0_ccm_encrypt;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
} else {
|
|
switch (mode) {
|
|
case CRYPTO_CIPHER_MODE_ECB:
|
|
LOG_ERR("ECB decryption not supported by the hardware");
|
|
return -EINVAL;
|
|
case CRYPTO_CIPHER_MODE_CTR:
|
|
ctx->ops.ctr_crypt_hndlr = crypto_cc23x0_ctr;
|
|
break;
|
|
case CRYPTO_CIPHER_MODE_CCM:
|
|
ctx->ops.ccm_crypt_hndlr = crypto_cc23x0_ccm_decrypt;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
ctx->ops.cipher_mode = mode;
|
|
ctx->device = dev;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int crypto_cc23x0_session_free(const struct device *dev,
|
|
struct cipher_ctx *ctx)
|
|
{
|
|
ARG_UNUSED(dev);
|
|
|
|
ctx->ops.ccm_crypt_hndlr = NULL;
|
|
ctx->device = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int crypto_cc23x0_query_caps(const struct device *dev)
|
|
{
|
|
ARG_UNUSED(dev);
|
|
|
|
return CRYPTO_CC23_CAP;
|
|
}
|
|
|
|
static int crypto_cc23x0_init(const struct device *dev)
|
|
{
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
const struct crypto_cc23x0_config *cfg = dev->config;
|
|
#endif
|
|
struct crypto_cc23x0_data *data = dev->data;
|
|
|
|
IRQ_CONNECT(DT_INST_IRQN(0),
|
|
DT_INST_IRQ(0, priority),
|
|
crypto_cc23x0_isr,
|
|
DEVICE_DT_INST_GET(0),
|
|
0);
|
|
irq_enable(DT_INST_IRQN(0));
|
|
|
|
CLKCTLEnable(CLKCTL_BASE, CLKCTL_LAES);
|
|
|
|
k_mutex_init(&data->device_mutex);
|
|
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
k_sem_init(&data->cha_done, 0, 1);
|
|
k_sem_init(&data->chb_done, 0, 1);
|
|
|
|
if (!device_is_ready(cfg->dma_dev)) {
|
|
return -ENODEV;
|
|
}
|
|
#else
|
|
k_sem_init(&data->aes_done, 0, 1);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static DEVICE_API(crypto, crypto_enc_funcs) = {
|
|
.cipher_begin_session = crypto_cc23x0_session_setup,
|
|
.cipher_free_session = crypto_cc23x0_session_free,
|
|
.query_hw_caps = crypto_cc23x0_query_caps,
|
|
};
|
|
|
|
static struct crypto_cc23x0_data crypto_cc23x0_dev_data;
|
|
|
|
#ifdef CONFIG_CRYPTO_CC23X0_DMA
|
|
static const struct crypto_cc23x0_config crypto_cc23x0_dev_config = {
|
|
.dma_dev = DEVICE_DT_GET(TI_CC23X0_DT_INST_DMA_CTLR(0, cha)),
|
|
.dma_channel_a = TI_CC23X0_DT_INST_DMA_CHANNEL(0, cha),
|
|
.dma_trigsrc_a = TI_CC23X0_DT_INST_DMA_TRIGSRC(0, cha),
|
|
.dma_channel_b = TI_CC23X0_DT_INST_DMA_CHANNEL(0, chb),
|
|
.dma_trigsrc_b = TI_CC23X0_DT_INST_DMA_TRIGSRC(0, chb),
|
|
};
|
|
|
|
DEVICE_DT_INST_DEFINE(0,
|
|
crypto_cc23x0_init,
|
|
NULL,
|
|
&crypto_cc23x0_dev_data,
|
|
&crypto_cc23x0_dev_config,
|
|
POST_KERNEL,
|
|
CONFIG_CRYPTO_INIT_PRIORITY,
|
|
&crypto_enc_funcs);
|
|
#else
|
|
DEVICE_DT_INST_DEFINE(0,
|
|
crypto_cc23x0_init,
|
|
NULL,
|
|
&crypto_cc23x0_dev_data,
|
|
NULL,
|
|
POST_KERNEL,
|
|
CONFIG_CRYPTO_INIT_PRIORITY,
|
|
&crypto_enc_funcs);
|
|
#endif
|