Jean-Paul Etienne 4b8ae8863c riscv32: riscv-privilege: Platform-Level Interrupt Controller support ... Updated the riscv-privilege SOC family to account for SOCs supporting a Platform-level Interrupt Controller (PLIC) as specified by the riscv privilege architecture. riscv-privilege SOCs supporting a PLIC have to implement the following list of APIs: void riscv_plic_irq_enable(uint32_t irq); void riscv_plic_irq_disable(uint32_t irq); int riscv_plic_irq_is_enabled(uint32_t irq); void riscv_plic_set_priority(uint32_t irq, uint32_t priority); int riscv_plic_get_irq(void); Change-Id: I0228574967348d572afc98a79257c697efc4309e Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>		2017-03-20 23:19:36 +00:00
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arc	Revert "sys_bitfield*(): use 'void *' instead of memaddr_t"	2017-02-28 16:06:22 -05:00
arm	arm: cortex-m: allow configurable ROM offset	2017-02-22 18:08:57 -06:00
nios2	Revert "sys_bitfield*(): use 'void *' instead of memaddr_t"	2017-02-28 16:06:22 -05:00
riscv32	riscv32: riscv-privilege: Platform-Level Interrupt Controller support	2017-03-20 23:19:36 +00:00
x86	Revert "sys_bitfield*(): use 'void *' instead of memaddr_t"	2017-02-28 16:06:22 -05:00
xtensa	kernel: add flexibility to k_cycle_get_32() definition	2017-02-16 19:27:59 +00:00
cpu.h	Xtensa port: Added support in arch/cpu.h for Xtensa cores.	2017-02-13 08:04:27 -08:00