Daniel Leung 1e7025c2e7 boards: intel_s1000_crb: fix setting cache attributes ... This reverts commit c9ace83c89 which bypasses setting cache attributes. The previous cache attributes actually set the text/data/etc. sections to be inaccessible. So fix it. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2019-02-15 16:21:50 -05:00
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arc	power: Fix naming of Kconfig options controlling deep sleep states	2019-02-12 07:46:32 -05:00
arm	arch: arm: mpu: get the region sizes from the linker	2019-02-13 06:58:01 -06:00
common	gen_isr_tables: Fix _sw_isr_table generation for multi-level IRQs	2019-02-06 10:13:25 -05:00
nios2	arch: Add 'U' to unsigned variable assignments	2018-12-04 22:51:56 -05:00
posix	tracing: POSIX arch: Trace switch to main thread	2019-02-14 15:41:19 -05:00
riscv32	arch: riscv32: Fix trivial comment	2019-01-31 07:40:24 -05:00
x86	x86: fix ROM permissions	2019-02-15 13:10:18 -08:00
x86_64	cmake: Use a variable for 'zephyr_prebuilt'	2019-01-19 07:21:55 -05:00
xtensa	boards: intel_s1000_crb: fix setting cache attributes	2019-02-15 16:21:50 -05:00
CMakeLists.txt	Build: Added support for out-of-tree Arch	2019-02-07 17:00:43 -05:00
Kconfig	power: Fix naming of Kconfig options controlling deep sleep states	2019-02-12 07:46:32 -05:00