Brett Witherspoon f8e812aa3f dts: arm: st: u5: correct lptim2 clock enable bit ... The LPTIM2 clock enable is bit 5 of RCC APB1 clock enable register 2 (RM0456 Rev 4 11.8.34). Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>		2023-10-09 10:17:07 +02:00
..
arc/synopsys	uart: ns16550: use io-mapped DT property for IO port access	2023-09-26 12:03:04 +02:00
arm	dts: arm: st: u5: correct lptim2 clock enable bit	2023-10-09 10:17:07 +02:00
arm64	dts: bindings: boards: Update Ethernet PHY to use reg property	2023-09-29 09:47:15 +02:00
bindings	dts: bindings: adxl372-i2c: update description	2023-10-08 11:17:02 +01:00
common
nios2/intel
posix
riscv	board: riscv: qemu: increase ndev of PLIC to 1024	2023-10-05 06:10:06 -04:00
sparc/gaisler	dts/sparc/gaisler: add SoC and board compatible strings	2023-05-02 10:53:27 +02:00
x86/intel	boards: x86: add eMMC support for Intel Alder lake platform	2023-09-29 16:29:00 +02:00
xtensa	dts: bindings: boards: Update Ethernet PHY to use reg property	2023-09-29 09:47:15 +02:00
binding-template.yaml
Kconfig