Andy Ross ae4f7a1a06 arch/xtensa: Remember to spill windows in arch_cohere_stacks() ... When we reach this code in interrupt context, our upper GPRs contain a cross-stack call that may still include some registers from the interrupted thread. Those need to go out to memory before we can do our cache coherence dance here. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-03-08 11:14:27 -05:00
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arc	arch: arc: fix mpu version number	2021-02-24 08:57:35 -05:00
arm	arch: arm64: select SCHED_IPI_SUPPORTED when SMP enabled	2021-03-06 07:36:37 -05:00
common	gen_isr_tables: Added check of the IRQ num before accessing the vt	2021-01-24 10:12:54 -05:00
nios2	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
posix	kernel: Add new k_thread_abort()/k_thread_join()	2021-02-24 16:39:15 -05:00
riscv	arch: riscv: add common stub reboot function	2021-03-04 11:09:51 -06:00
sparc	Revert "lib/os/heap: introduce option to force big heap mode"	2021-02-19 07:32:22 -05:00
x86	x86: gen_idt: fix some pylint issues	2021-03-03 20:10:22 -05:00
xtensa	arch/xtensa: Remember to spill windows in arch_cohere_stacks()	2021-03-08 11:14:27 -05:00
CMakeLists.txt	cmake: fix include directories to work with out-of-tree arch	2020-08-05 08:06:07 -04:00
Kconfig	arch/xtensa: Inline atomics	2021-03-08 11:14:27 -05:00