112cd172c1
Current Implementation to write to MAC_MDIO_ADDRESS causes CR to be set to 0. This leads to the divide always being 42 (on FRDM_MCXN947) so, by default the clock is running at ~3.6MHz which is out of spec range (1.0-2.5MHz) This stops the do_transaction function from overwriting CR. It also saves off the CR register before DMA reset Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com> |
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| .. | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.adin2111 | ||
| Kconfig.dwcxgmac | ||
| Kconfig.esp32 | ||
| Kconfig.gpio | ||
| Kconfig.lan865x | ||
| Kconfig.litex | ||
| Kconfig.nxp_enet | ||
| Kconfig.nxp_enet_qos | ||
| Kconfig.nxp_imx_netc | ||
| Kconfig.nxp_s32_gmac | ||
| Kconfig.nxp_s32_netc | ||
| Kconfig.renesas_ra | ||
| Kconfig.sam | ||
| Kconfig.stm32_hal | ||
| Kconfig.sy1xx | ||
| Kconfig.xilinx_axienet | ||
| Kconfig.xmc4xxx | ||
| mdio_adin2111.c | ||
| mdio_dwcxgmac.c | ||
| mdio_esp32.c | ||
| mdio_gpio.c | ||
| mdio_lan865x.c | ||
| mdio_litex_liteeth.c | ||
| mdio_nxp_enet_qos.c | ||
| mdio_nxp_enet.c | ||
| mdio_nxp_imx_netc.c | ||
| mdio_nxp_s32_gmac.c | ||
| mdio_nxp_s32_netc.c | ||
| mdio_renesas_ra.c | ||
| mdio_sam.c | ||
| mdio_shell.c | ||
| mdio_stm32_hal.c | ||
| mdio_sy1xx.c | ||
| mdio_xilinx_axienet.c | ||
| mdio_xmc4xxx.c | ||